An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Switch Circuit and Method of Switching Radio Frequency Signals

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

Integrated RF front end with stacked transistor switch

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

Method and Apparatus Improving Gate Oxide Reliability by Controlling Accumulated Charge

A push-pull switch including a first N-channel MOS transistor, the drain-source path of which is connected between a high voltage terminal and an output terminal, a first resistor connected between the gate of the first transistor and the high voltage, a diode having its anode connected to the output terminal and its cathode connected to the gate of the first transistor, a second N-channel MOS transistor having its drain connected to the cathode of the diode, its source connected to a reference potential, and its gate connected to a control terminal, and a second resistor connected between the gate of the second transistor and the output terminal.

very high voltage switch

The present invention relates to a flat display screen, comprising a cathode with electron emission microtips associated with a grid for extracting electrons from the microtips, the cathode/grid comprising conductive grid or cathode lines adapted to being sequentially addressed, and cathode or grid columns perpendicular to the lines and adapted to being addressed individually and simultaneously during the addressing of a line, and the screen comprising a return electrode adapted to being biased to a return potential corresponding to a no electron emission potential, each grid or cathode line being connected, via at least one resistive element, to the return electrode.

Flat display screen including a cathode having electron emission microtips associated with a grid for extracting electrons from the microtips

The display screen has a micro-point cathode emitting electrons and an associated grid to extract the electrons. The cathode/grid is formed from conductive rows (15') which can be addressed sequentially and perpendicular columns (14') that can be addressed individually and simultaneously during addressing of the rows. A return electrode (30) set to a positive potential is connected via a resistance to each grid or cathode row.

Simplification of the addressing of a microtips display with resetting electrode

L'invention concerne un ecran plat de visualisation, comportant une cathode a micropointes d'emission electronique associee a une grille d'extraction d'electrons des micropointes, la cathode/ grille comprenant des lignes conductrices (15') de grille ou de cathode propres a etre adressees sequentiellement et des colonnes (14') de cathode ou de grille perpendiculaires auxdites lignes et propres a etre adressees individuellement et simultanement pendant l'adressage d'une ligne, et l'ecran comportant une electrode de rappel (30) propre a etre polarisee a un potentiel de rappel (+Vl) correspondant a un potentiel d'absence d'extraction d'electrons, chaque ligne de grille ou de cathode etant reliee, par l'intermediaire d'au moins un element resistif (11), a l'electrode de rappel.

Philippe Peyron

Papers

very high voltage switch

Flat display screen including a cathode having electron emission microtips associated with a grid for extracting electrons from the microtips

Simplification of the addressing of a microtips display with resetting electrode

Simplification de l'adressage d'un ecran a micropointes