An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A method of fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface (12), forming on the surface (12) of the silicon substrate (10), by atomic layer deposition (ALD), a seed layer (20;20') characterised by a silicate material and forming, by atomic layer deposition (ALD) one or more layers of a high dielectric constant oxide (40) on the seed layer (20;20').

Method for fabricating a semiconductor structure including a metal oxide interface with silicon

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Dense arrays and charge storage devices

A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel direction. The impurity regions 104 are effective in suppressing the short channel effects. More specifically, the impurity regions 104 suppress expansion of a drain-side depletion layer, so that the punch-through phenomenon can be prevented. Further, the impurity regions cause a narrow channel effect, so that reduction in threshold voltage can be lessened.

Semiconductor device having an SOI structure and manufacturing method therefor

An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Switch Circuit and Method of Switching Radio Frequency Signals

An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD current for a wider unsegmented device.

Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility

A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact and the device body in which the voltage controlled channel is located. Several efficient connections using through hole plating or polycrystalline silicon gate extension are disclosed. A higher power supply voltage can be used by interconnecting the gate and device body through a smaller MOSFET.

Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation

A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact (20) and the device body (14) in which the voltage controlled channel is located. Several efficient connections using through hole plating or polycrystalline silicon gate extension are disclosed. A higher power supply voltage can be used by interconnecting the gate and device body through a smaller MOSFET.

Dynamic threshold voltage mosfet for ultra-low voltage operation

http://ieeexplore.ieee.org/iel1/55/4974/00192820.pdf

Improvement of Charge Trapping Char act er is tics of N, 0- Annealed and Reoxidized N,O-Annealed Thin Oxides

A Silicon-On-Insulator, fully-complementary BiCM[OS process has been developed for realizing high-performance circuit operation in the sub-3.3V power supply regime. Complementary, double-diffused lateral BJTs and fullyoverlapped, asymmetrical DDD MOSFETs have been successfully integrated in a 10-mask process by utilizing the process simplifications that are unique to thin-film !SO1 substrates. The BJTs exhibit the highest lateral current gains reported to date, with hfe=120 and 225 for the NPN and PNP, respectively. NPN ft=4.5GHi was achieved, and ft>20GHz is possible with an improved layout. 'me MOSFETs demonstrate excellent short-channel behavior down to Lef~0.18~, with Tox=lOnm. The p+ gate, !SO1 PMOS device exhibits superior Iht and gmsat. A record propagation delay of 12ps/stage at vdd=Sv and 300K was obtained for the CMOS ring oscillators fabricated in ithis technology. This demonstrates the performance achievea.ble with a deep-sub-micron SO1 process.

Ping K. Ko

Papers

Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility

Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation

Dynamic threshold voltage mosfet for ultra-low voltage operation

Improvement of Charge Trapping Char act er is tics of N, 0- Annealed and Reoxidized N,O-Annealed Thin Oxides

A Versatile, SO4 BiCMOS Technology with Complenientary Lateral B JT's