Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for inter- and intra-die process variations and their spatial correlations. Since statistical timing analysis has an exponential run time complexity, we propose a method whereby a statistical bound on the probability distribution function of the exact circuit delay is computed with linear run time. First, we develop a model for representing inter- and intra-die variations and their spatial correlations. Using this model, we then show how gate delays and arrival times can be represented as a sum of components, such that the correlation information between arrival times and gate delays is preserved. We then show how arrival times are propagated and merged in the circuit to obtain an arrival time distribution that is an upper bound on the distribution of the exact circuit delay. We prove the correctness of the bound and also show how the bound can be improved by propagating multiple arrival times. The proposed algorithms were implemented and tested on a set of benchmark circuits under several process variation scenarios. The results were compared with Monte Carlo simulation and show an accuracy of 3.32% on average over all test cases.

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Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations

As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunately, current error correction techniques are poorly suited to this emerging class of memory technologies. Unlike DRAM, PCM and other resistive memories have wear lifetimes, measured in writes, that are sufficiently short to make cell failures common during a system's lifetime. However, resistive memories are much less susceptible to transient faults than DRAM. The Hamming-based ECC codes used in DRAM are designed to handle transient faults with no effective lifetime limits, but ECC codes applied to resistive memories would wear out faster than the cells they are designed to repair. This paper evaluates Error-Correcting Pointers (ECP), a new approach to error correction optimized for memories in which errors are the result of permanent cell failures that occur, and are immediately detectable, at write time. ECP corrects errors by permanently encoding the locations of failed cells into a table and assigning cells to replace them. ECP provides longer lifetimes than previously proposed solutions with equivalent overhead. What's more, as the level of variance in cell lifetimes increases -- a likely consequence of further scalaing -- ECP's margin of improvement over existing schemes increases.

/pdf/use-ecp-not-ecc-for-hard-failures-in-resistive-memories-2kqigkjllz.pdf

Use ECP, not ECC, for hard failures in resistive memories

Process variations are of increasing concern in today's technologies, and they can significantly affect circuit performance An efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both inter-die and intra-die variations, while accounting for the effects of spatial correlations of intra-die parameter variations, is presented The procedure uses a first-order Taylor series expansion to approximate the gate and interconnect delays Next, principal component analysis (PCA) techniques are employed to transform the set of correlated parameters into an uncorrelated set The statistical timing computation is then easily performed with a program evaluation and review technique (PERT)-like circuit graph traversal The run time of this algorithm is linear in the number of gates and interconnects, as well as the number of varying parameters and grid partitions that are used to model spatial correlations The accuracy of the method is verified with Monte Carlo (MC) simulation On average, for the 100 nm technology, the errors of mean and standard deviation (SD) values computed by the proposed method are 106% and -434%, respectively, and the errors of predicting the 99% and 1% confidence point are -246% and -099%, respectively A testcase with about 17 800 gates was solved in about 500 s, with high accuracy as compared to an MC simulation that required more than 15 h

/pdf/statistical-timing-analysis-under-spatial-correlations-2lyd263iwu.pdf

Statistical timing analysis under spatial correlations

Ultra-deep submicron manufacturability impacts physical design (PD) through complex layout rules and large guard-bands for process variability; this creates new requirements for new manufacturing-aware PD technologies. The first part of this tutorial reviews PD complications and methodology changes notably in the detailed routing arena - that arise from subwavelength lithography and deep-submicron manufacturing (antennas, metal planarization and mask-wafer mismatch). Process variations and their sources are taxonomized for modeling and simulation. A framework of design for cost and value is described. The second part covers yield-constrained optimizations in PD, especially "beyond corners" approaches that escape today's pessimistic or even incorrect corner-based approaches. Statistical timing and noise analyses enable optimization of parametric yield and reliability. Yield-aware cell libraries and "analog" design rules (as opposed to "digital", 0/1 rules) can help designers explore yield-cost tradeoffs, especially for low-volume parts. We then examine performance impact-limited fill insertion which goes beyond mere capacitance rules. Modeling, objectives, and filling strategies are discussed. Finally, we discuss current and near-term prospects for the overall design-to-manufacturing PD methodology. Key aspects include better integrations with analysis and manufacturing interfaces, as well as cost-benefit tradeoffs for "regular" layout structures that are likely beyond 90 nm, cost optimizations for low-volume production, and the role of robust and/or stochastic optimization in PD.

/pdf/manufacturing-aware-physical-design-4w9fis5ea3.pdf

Manufacturing-Aware Physical Design

Within-die spatial correlation of device parameter values caused by manufacturing variations has a significant impact on circuit performance. Based on experimental and simulation results, we: (1) characterize the spatial correlation of gate length over a full-field range of horizontal and vertical separation; (2) develop a rudimentary spatial correlation model; and (3) investigate its impact an the variability of circuit performance.

Modeling within-die spatial correlation effects for process-design co-optimization

In this paper we address both empirically and theoretically the impact of an advanced manufacturing phenomenon on the performance of high-speed digital circuits. Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18-/spl mu/m CMOS process. The measured data revealed a significant systematic, rather than random spatial intrachip variability of MOS gate length, leading to large circuit path delay variation. The delay of the critical path of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. We demonstrate explicitly that intrachip Lgate variation has a significant detrimental impact on the overall circuit performance, shifting the entire distribution of clock frequencies toward slower values. This is in striking contrast to the impact of interchip Lgate variation, traditionally considered in statistical circuit analysis, which leads to the variation of chip clock frequencies around the average value. Moreover, analysis shows that the spatial, rather than proximity-dependent systematic Lgate variability, is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows mitigation of the detrimental effects of Lgate variability and have developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of practical implementation of the methodology, and provide guidelines for managing design complexity.

https://www.cerc.utexas.edu/robust/publications/2002/impact_systemac_var_performnace_tcad02.pdf

Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits

Accurate noise analysis is currently of significant concern to high-performance designs, and the number of signals susceptible to noise effects will certainly increase in smaller process geometries. Our approach uses a combination of temporal and functional information to eliminate false transition combinations and thereby overcome insufficiencies in static noise analysis. A similar idea arises in timing analysis where functional and timing information is used to eliminate false paths. The goal of our work is to develop an algorithm, software tool, and noise analysis flow that provide an accurate and conservative approach to noise analysis. In particular, this paper proposes an approach to identifying a pair of vectors that exercises the maximum crosstalk noise.

/pdf/towards-true-crosstalk-noise-analysis-5c7j0uu0rc.pdf

Towards true crosstalk noise analysis

In coupling delay computation, a Miller factor of more than 2/spl times/ may be necessary to account for active coupling capacitance when modeling the delay of deep submicron circuitry in the presence of active coupling capacitance. We propose an efficient method to estimate this factor such that the delay response of a decoupling circuit model can emulate the original coupling circuit. Under the assumptions of zero initial voltage, equal charge transfer, and 0.5V/sub DD/ as the switching threshold voltage, an upper bound of 3/spl times/ for maximum delay and a lower bound of -1/spl times/ for minimum delay can be proven. Efficient Newton-Raphson iteration is also proposed as a technique for computing the Miller factor or effective capacitance. This result is highly applicable to crosstalk coupling delay calculation in deep submicron gate-level static timing analysis. Detailed analysis and approximation are presented. SPICE simulations are demonstrated to show high correlation with these approximations.

Miller factor for gate-level coupling delay calculation

Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18 /spl mu/m CMOS process. The measured data revealed significant systematic, rather than random, spatial intra-chip variability of MOS gate length, leading to large circuit path delay variation. The critical path value of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error (/spl sim/25%) and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. Analysis shows that the spatial, rather than proximity-dependent, systematic Lgate variability is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows to mitigate the detrimental effects of Lgate variability, and developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of the practical implementation of the methodology, and provide the guidelines for managing the design complexity.

https://www.cerc.utexas.edu/robust/publications/2000/systematic_spatial%20variability_iccad00.pdf

Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits

Crosstalk effect is crucial for timing analysis in very deep submicron design. In this paper, we present and compare multiple scheduling algorithms to compute switching windows for static timing analysis in presence of crosstalk noise. We also introduce an efficient technique to evaluate the worst case alignment of multiple aggressors.

Pinhong Chen

Papers

Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits

Towards true crosstalk noise analysis

Miller factor for gate-level coupling delay calculation

Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits

Switching window computation for static timing analysis in presence of crosstalk noise