When designing embedded systems, especially for space-computing needs, finding the ideal balance between size, weight, power, and cost (SWaP-C) is a primary goal in the processor selection process. One variable that can have a significant impact on the tradeoffs between performance and power consumption is the processor architecture. Widely adopted architectures such as the ARM Cortex-A series have gained popularity due to their favorable combination of high performance and low power consumption. The RISC-V architecture presents a compelling alternative in part due to its modular instruction set, collaborative development approach, and open-source nature. The recent introduction of a RISC-V processor in the Microchip PolarFire SoC enables performance and power consumption comparisons with competing architectures using application and kernel benchmarks. For application benchmarking, this research employs several image-processing applications, including a histogram equalizer, Sobel filter, and image tiler, to describe real-world device performance. To gain additional insight into a processor’s architectural characteristics, kernel benchmarks that perform common operations in sensor processing such as matrix multiplication and convolution are used. In addition, the CoreMark synthetic benchmark suite is used to help quantify overall performance. This study considers several architectures and space-grade computer facsimiles, including the ARM Cortex-A9 SHREC Space Processor, the ARM Cortex-A53 Boeing High Performance Space Computing platform, and the Power e5500 BAE Systems RAD5545 processor. Both single- and multi-core performance are considered. The PolarFire SoC achieves approximately 3.13 CoreMarks per MHz and 15.63 CoreMarks per milliwatt, demonstrating competitive performance and power consumption characteristics under single-threaded workloads. However, RISC-V presents mixed results in kernel and application benchmarks incorporating multiprocessing, with execution times that are average at best. Additionally, while matrix multiplication and addition yield high parallel efficiencies, matrix convolution and transpose are less efficient. Dynamic energy consumption results for the PolarFire SoC were generally average, but the platform does achieve significant reductions in dynamic energy consumption during increased parallel workloads in some tests. Dynamic energy consumption variability was also very low for the PolarFire SoC during most benchmarks. While the RISC-V architecture does not present ideal benchmark results, it provides a competitive balance between performance and power consumption, with future extensions to the instruction set only further enabling its potential for space applications.

RISC-V Benchmarking for Onboard Sensor Processing

This paper introduces an efficient and simple implementation of management methodology between two RvCores (32-bit) microprocessor to manage the parallel processing to support multi-core processor. In hardware level, a peripheral unit has been developed to manage timing of operations between the two cores without making any disturbance to the default working core in addition to some important future work that will be executed on this device for more enhancement. Under test techniques: unit, integration and system tests, extensive tests and testbenches have been created for each type of test on the corresponding design to check the correctness of operations. On system test, a dual-core task has been developed by C language to check the output correct result. Additionally, the performance of the processor has been shown in number of executed clock cycles. 

Dual-RvCore32IMA: Implementation of a Peripheral Device to Manage Operations of Two RvCores

A processor is the core component of an electronic system. In this work, we present a high-performance general-purpose processor system, based on open source RISC-V instruction set architecture. Our processor has a 32-bit 5-stage pipeline core with separate 8 KB I-Cache and D-Cache, and supports virtual memory system. The processor supports integer, atomic and floating-point (single and double precision) instruction subset of RISC-V ISA. The nested vectored interrupt unit and the dedicated floating-point execution unit is included in the system to improve its real-time performance. To improve the execution speed of the processor, a branch prediction unit and a hardware Economic Value Added replacement policy for I-Cache and D-Cache is implemented. The performance of processor is evaluated using CoreMark and has a CoreMark value of 3.32 CoreMark/MHz. The design is implemented on Xilinx's Virtex-7 (XC7VX485tffg1761-2) FPGA and has maximum clock frequency of 60MHz.

Piyush Birla

Papers

A RISC-V ISA Compatible Processor IP