A semiconductor device includes a plurality of semiconductor fins, an epitaxy structure, a capping layer, and a contact. The epitaxy structure adjoins the semiconductor fins. The epitaxy structure has a plurality of protrusive portions. The capping layer is over a sidewall of the epitaxy structure. The contact is in contact with the epitaxy structure and the capping layer. The contact has a portion between the protrusive portions. The portion of the contact between the protrusive portions has a bottom in contact with the epitaxy structure.

Semiconductor device and method for fabricating the same

Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively removing a first region of a silicon material between source/drain regions of a semiconductor substrate to expose a first region of oxide material. The methods may include forming a liner over the first region of oxide material and contacting second regions of the silicon material proximate the source/drain regions of the semiconductor substrate. The methods may also include selectively removing the second regions of the silicon material proximate the source/drain regions of the semiconductor substrate to expose a second region of the oxide material. The methods may further include selectively removing the second region of the oxide material from a surface of a contact in the semiconductor structure.

Replacement contact process

In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

Method of manufacturing a semiconductor device and a semiconductor device

Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.

Gate metal patterning for tight pitch applications

Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include a mixing manifold coupled between the remote plasma unit and the processing chamber. The mixing manifold may be characterized by a first end and a second end opposite the first end, and may be coupled with the processing chamber at the second end. The mixing manifold may define a central channel through the mixing manifold, and may define a port along an exterior of the mixing manifold. The port may be fluidly coupled with a first trench defined within the first end of the mixing manifold. The first trench may be characterized by an inner radius at a first inner sidewall and an outer radius, and the first trench may provide fluid access to the central channel through the first inner sidewall.

Semiconductor processing chamber multistage mixing apparatus and methods

A semiconductor device including a first substrate and a thin film transistor disposed on the first substrate is provided The thin film transistor includes a gate, a semiconductor pattern, a first insulating layer, a source and a drain The first insulating layer is disposed between the gate and the semiconductor pattern The source and the drain are separated from each other and disposed corresponding to the semiconductor pattern At least one of the source and the drain has a first copper patterned layer and a first copper oxynitride patterned layer The first copper oxynitride patterned layer covers the first copper patterned layer The first copper patterned layer is disposed between the first copper oxynitride patterned layer and the first substrate Moreover, a manufacturing method of the semiconductor device is also provided

Semiconductor device and manufacturing method thereof

An active device structure and a method of fabricating an active device are provided. The active device structure includes a gate, an oxide channel layer, a source, a drain and a high power deposited insulation layer. The gate and the oxide channel layer are overlapped in a top and bottom manner. The oxide channel layer includes a top layer and a bottom layer having a crystalline structure different from a crystalline structure of the top layer. The source and the drain both contact the oxide channel layer, wherein a gap separating the source and the drain defines a channel area. The high power deposited insulation layer contacts the top layer of the oxide channel layer. The top layer of the oxide channel layer provides the effect of blocking light, which solves the problem of threshold voltage shift due to the light irradiation on the oxide channel layer.

Active device structure and fabricating method thereof

Active device structure with oxide channel layer having degree of crystallinity and method thereof

The invention relates to a semiconductor structure and a manufacturing method thereof The semiconductor structure is configured on a substrate and comprises a first metal layer arranged on the substrate, a gate insulating layer arranged on the substrate, an oxide semiconductor layer arranged on the gate insulating layer, an etching barrier pattern arranged on the oxide semiconductor layer and a second metal layer arranged on the etching barrier pattern The first metal layer includes a gate line The gate insulating layer covers the gate line The patterning of the oxide semiconductor layer defines an oxide semiconductor pattern The second metal layer includes a source and a drain electrically connected to the oxide semiconductor pattern A portion of the etch stop pattern is between thesecond metal layer and the oxide semiconductor layer The second metal layer further includes a signal line disposed on the etch stop pattern and electrically connected to the oxide semiconductor pattern The invention also provides a manufacturing method of the semiconductor structure

Po-Liang Yeh

Papers

Semiconductor device and manufacturing method thereof

Active device structure and fabricating method thereof

Active device structure with oxide channel layer having degree of crystallinity and method thereof

Semiconductor structure and manufacturing method thereof