A method of fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface (12), forming on the surface (12) of the silicon substrate (10), by atomic layer deposition (ALD), a seed layer (20;20') characterised by a silicate material and forming, by atomic layer deposition (ALD) one or more layers of a high dielectric constant oxide (40) on the seed layer (20;20').

Method for fabricating a semiconductor structure including a metal oxide interface with silicon

A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon carbide substrate and with at least one metal contact for the device on the first surface of the substrate. The opposite, second surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished second surface of the silicon carbide substrate to define a predetermined location for a via that is opposite the device metal contact on the first surface; etching the desired via through the desired masked location until the etch reaches the metal contact on the first surface; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.

Method of forming vias in silicon carbide and resulting devices and circuits

In another preferred form of the present invention, there is provided a method for determining the risk of rupture of a blood vessel using an appropriate set of 2-D slice images obtained by scanning the blood vessel, the method comprising: generating a mesh model of the blood vessel using the set of 2-D slice images; conducting finite element stress analysis on the mesh model to calculate the level of stress on different locations on the mesh model; and determining the risk of rupture of the blood vessel based on the calculated levels of stress on different locations on the mesh model. In another preferred form of the present invention, there is provided an apparatus for determining the risk of rupture of a blood vessel using an appropriate set of 2-D slice images obtained by scanning the blood vessel, the apparatus comprising: apparatus for generating a mesh model of the blood vessel using the set of 2-D slice images; apparatus for conducting finite element stress analysis on the mesh model to calculate the level of stress on different locations on the mesh model; and apparatus for determining the risk of rupture of the blood vessel based on the calculated levels of stress on different locations on the mesh model.

Anatomical visualization and measurement system

Embodiments of the invention provide methods for depositing a capping layer on a dielectric layer disposed on a substrate. In one example, a process includes exposing a substrate to a deposition process to form a dielectric layer thereon, exposing the substrate to sequential pulses of a silicon precursor and an oxidizing gas to form a silicon-containing layer on the dielectric layer during a deposition process, exposing the substrate to a nitridation process to form a capping layer thereon and exposing the substrate to an annealing process for a predetermined time. The capping layer may a thickness of about 5 A or less. In one example, the oxidizing gas contains water vapor derived from a hydrogen source gas and an oxygen source gas processed by a water vapor generator containing a catalyst. In another example, the deposition, nitridation and annealing processes occur in the same process chamber.

Formation of a silicon oxynitride layer on a high-k dielectric material

Embodiments of the invention provide methods for forming hafnium materials, such as oxides and nitrides, by sequentially exposing a substrate to hafnium precursors and active oxygen or nitrogen species (e.g., ozone, oxygen radicals, or nitrogen radicals). The deposited hafnium materials have significantly improved uniformity when deposited by these atomic layer deposition (ALD) processes. In one embodiment, an ALD chamber contains an expanding channel having a bottom surface that is sized and shaped to substantially cover a substrate positioned on a substrate pedestal. During an ALD process for forming hafnium materials, process gases form a vortex flow pattern while passing through the expanding channel and sweep across the substrate surface. The substrate is sequentially exposed to chemical precursors that are pulsed into the process chamber having the vortex flow.

Ald metal oxide deposition process using direct oxidation

The present invention relates to a gate stack structure having a dielectric material layer disposed on a substrate with a gate electrode disposed thereon. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.2 nm or less and includes at least one layer other than silicon dioxide. Furthermore, the dielectric material layer of the present invention enables device scaling and provides (1) decreased leakage current and improved tunneling voltage compared to a conventional gate dielectric; and (2) avoids the perils of ultra-thin silicon dioxide when used exclusively as the gate dielectric.

Gate structure for integrated circuit fabrication

A method of fabricating an integrated circuit device includes forming a first metal oxide layer adjacent a semiconductor substrate. The first metal oxide layer may be formed of tantalum oxide, for example. A second metal oxide layer, which includes an oxide with a relatively high dielectric constant such as titanium oxide, zirconium oxide, or ruthenium oxide, is formed on the first metal oxide layer opposite the semiconductor substrate, and a metal nitride layer, such as titanium nitride, is formed on the metal oxide layer opposite the first metal oxide layer. The metal nitride layer includes a metal which is capable of reducing the metal oxide of the first metal oxide layer. Thus, the second metal oxide layer substantially blocks reduction of the metal oxide of the first metal oxide layer by the metal of the metal nitride layer.

Methods of fabricating an integrated circuit device with composite oxide dielectric

A polishing pad formed from closed-cell elastomer foam includes a population of bubbles within the pad As the pad wears due to polishing and the polishing surface recedes, the freshly formed polishing surface includes pores formed of the newly exposed bubbles The pores receive and retain polishing slurry and aid in the chemical mechanical polishing process Pad conditioning is not required because new pores are constantly being created at the pad surface as the surface recedes during polishing The method for forming the polishing pad includes the injection of gas bubbles into the viscous elastomer material used to form the pad Process conditions are chosen to maintain gas bubbles within the elastomer material during the curing and solidifying process steps

Polishing pads from closed-cell elastomer foam

A chemical mechanical polishing (CMP) system includes a polishing device including a polishing article. The polishing device provides relative movement between the semiconductor wafer and the polishing article with a slurry therebetween. The slurry preferably includes abrasive particles and a photocatalyst to enhance oxidation of metal of the semiconductor wafer. The slurry may also include water and the photocatalyst is a mixed metal oxide for breaking down water into hydrogen and oxygen in the presence of light.

CMP system and slurry for polishing semiconductor wafers and related method

A titanium nitride barrier within an integrated contact structure is formed as multi-layered stack. The multi-layering of the titanium nitride thus provides improved junction integrity since the multi-layer structure exhibits improved mechanical stability when compared to conventional single layer arrangements. The multi-layer titanium nitride barrier may be used as either a conventional interconnect metallization or as a nucleation structure within a tungsten plug. The multi-layer structure may be formed to include an overall thickness less than a conventional single layer, yet provide for improved stress accommodation, resulting in eliminating micro-cracks within the titanium nitride (and as a result eliminating the un-wanted diffusion of aluminum or tungsten precursors through the titanium nitride).

Pradip Kumar Roy

Papers

Gate structure for integrated circuit fabrication

Methods of fabricating an integrated circuit device with composite oxide dielectric

Polishing pads from closed-cell elastomer foam

CMP system and slurry for polishing semiconductor wafers and related method

Multi-layered titanium nitride barrier structure