Scan testing and scan compression are key to realizing cost reduction and quality control of ever more complex designs. However, compression can be limited if the density of unknown (X) values is high. We present a method to identify a small, but important, subset of scan cells that are "likely" to capture an X, place them on separate "X-chains", create a combinational unload compressor tuned for these X-chains, and modify test generation to take advantage of this circuit. This method is fully integrated in the design-for-test (DFT) flow, requires no additional user input and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.

Increasing Scan Compression by Using X-chains

Electronic scan circuitry includes a decompressor ( 510 ), a plurality of scan chains ( 520. i ) fed by the decompressor ( 510 ), a scan circuit ( 502, 504 ) coupled to the plurality of scan chains ( 520. i ) to scan them in and out, a masking circuit ( 590 ) fed by the scan chains ( 520. i ), and a scannable masking qualification circuit ( 550, 560, 580 ) coupled to the masking circuit ( 590 ), the masking qualification circuit ( 550, 560, 580 ) scannable by scan-in of bits by the decompressor ( 510 ) along with scan-in of the scan chains ( 520. i ), and the scannable masking qualification circuit ( 550, 560, 580 ) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit ( 590 ). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems

A method and system to estimate failure rates in designs. A set of N Monte Carlo samples (points) are drawn from the random distribution that describes process variation in the design. Then, a subset of these samples is selected, and that subset of Ninit samples are simulated (with a circuit simulator) to measure a performance value for each sample. Then, a model is constructed, using the values of the Ninit process points as training inputs, and the corresponding Ninit performance values as training outputs. The candidate Monte Carlo samples are from the N Monte Carlo samples that have not yet been simulated. Each candidate is simulated on the model to get predicted performance values, and the samples are ordered in ascending (or descending) order of the predicted performance values. Simulation of candidates samples is then begun, in that order. The model and ordering may be periodically updated. The sampling and simulation will stop once there is sufficient confidence that all failures are found.

Method and system for identifying rare-event failure rates

Embodiments of the present invention provide methods and apparatuses for implementing hierarchical design-for-test (DFT) logic on a circuit. The hierarchical DFT logic implements DFT circuitry that can be dedicated to a module, and which can configure DFT circuitry for multiple modules to share a sequential input signal and/or to share a sequential output signal. During operation, the DFT circuitry for a first module can propagate a bit sequence from the sequential input signal to the DFT circuitry of a second module, such that the bit sequence can include a set of control signal values for controlling the DFT circuitry, and can include compressed test vectors for testing the modules. Furthermore, the DFT circuitry for the second module can generate a sequential response signal, which combines the compressed response vectors from the second module and a sequential response signal from the DFT circuitry of the first module.

Method and apparatus for implementing a hierarchical design-for-test solution

This paper presents a novel framework comprises of a Propositional Satisfiability (SAT) encoder and solver. The framework responsible for generating and proving a simplified SAT-based formula of digital circuits for Automatic Test Pattern Generation (ATPG) proposes. The parallel algorithms introduced in this work are aimed at both combinational and sequential circuits and optimized on NVIDIA General-Purpose Graphics Processing Unit (GPGPU) paradigm. The SAT encoder presents an efficient method to apply the Boolean Constraint Propagation (BCP) on-the-fly while the generation is running on the GPU. The simplified formula is further proved for satisfiability using an improved parallel solver on GPU. The proposed encoder executes 93 times faster compared to the sequential counterpart. The test generation algorithm using the GPU-accelerated framework delivers about 5.86 speedup on an average compared to the state-of-the-art Lingeling solver. Moreover, the SAT encoder reduced the run time for fault detection by 6.53 and 11.42% on an average when applied to the proposed and the conventional CUD@SAT solvers, respectively, offering promising related work for the future research.

An Efficient SAT-Based Test Generation Algorithm with GPU Accelerator

Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design.

Test design optimizer for configurable scan architectures

To leverage the computing power of multicore machines in ATPG, we developed a highly efficient parallel ATPG system based on dynamic fault partition and shared memory. The system takes advantage of built-in efficiency of parallel search to achieve good performance speedup with no sacrifices in pattern quality or test coverage.

Highly efficient parallel ATPG based on shared memory

STMicroelectronics has been using scan compression for many years. With the vast variety of designs and the size of the company it is important to deploy an easy to use solution that works for all the conditions. Today we support many different compression schemes DFTMAX, DFTMAX Xtol, Serializer. Each of these solutions is strong in a segment of the designs. DFTMAX Ultra has a technology that provides a single solution for all needs. In this paper we discuss the variety of design scenarios seen in ST from the point of scan compression. Results of DFTMAX Ultra are then presented to show that it is a viable unified solution.

Pramod Notiyath

Papers

Test design optimizer for configurable scan architectures

Highly efficient parallel ATPG based on shared memory

Unifying scan compression

DFT MAX and Power

Testdesignoptimierer für konfigurierbare scanarchitekturen