This paper reports a new design of a low power two stage operational amplifier with Miller compensated topology for enhancing stability. The circuit is designed and simulated in Tanner EDA tool using 45 nm. CMOS technology. A significant reduction in power and enhancement of unity gain BW is achieved with a satisfactory phase margin. Several parameters are computed and compared with a few contemporary works to establish the efficacy of the design.

Design of an low power miller compensated two stage OP-AMP using 45 nm technology for high data rate communication

The voltage and the current references are important blocks in analog VLSI circuits. The temperature fluctuations, operating voltage and load currents are remains constant by using the voltage reference circuits. The bipolar transistors and resistors are used in traditional bandgap reference circuits, these are consuming more area and power hence to buried this drawback, we build a resistorless bandgap reference using MOSFETs and generating a negative temperature coefficient MOSFETs are operating in sub threshold region and the inversion technique is used to received the gain. This circuit works on voltage of 1.2v and −10°c to 120°c is temperature range with temperature coefficient 4.5ppm/c. This bandgap reference circuit is implemented by cadence tool CMOS 180nm (UMCI80) technology. The silicon area is 0.027mm2.

Design of Resistorless Bandgap Reference

The voltage reference circuits are an important part of analog and mixed-signal VLSI systems. Voltage reference circuits generate constant voltage independent of temperature and supply-voltage variations. In the conventional Bandgap References (BGR) output voltage is the sum of the forward voltage drop across a diode and thermal voltage multiplied by constant. This paper proposes BGR circuit design in 180 nm technology that operates on a 3.3 V power supply and generates 1.20 V for the temperature range -$40^{\circ}\mathrm{C}$ to $140^{\circ}\mathrm{C}$ with a temperature coefficient of 12.71 ppm/oC. The layout of the proposed work is developed, and the simulation results postlayout are matched with pre-layout. The proposed Bandgap Reference (BGR) design uses only MOSFETs and BJTs. The design is analyzed theoretically and practically. The output reference voltage is observed in pre-layout and post-layout simulations using sky130 PDK The proposed design consumes 72.6 $\mu \mathrm{W}$ of power.

Design of Start-up Enabled Bandgap Voltage Reference

A reference generator provides a reference output voltage that is continuously available while providing certain efficiencies of a duty-cycled voltage regulator The reference output voltage is generated by a sample-and-hold circuit that is coupled to a voltage regulator On command, the sample-and-hold circuit samples a low dropout voltage regulator that may be referenced by a bandgap circuit During hold periods of the sample-and-hold circuit, the voltage regulator, in particular the bandgap circuit, may be disabled in order to conserve power A sample cycle by the sample-and-hold circuit may be triggered by a signal received from a configurable finite state machine The reference generator is effectively duty cycled in a manner that conserves available battery power, while still providing a constant reference output that is always available The reference generator is especially suited for low-power, battery operated applications

Circuit and method for generating a reference voltage with a voltage regulator and a sample and hold circuit

The present work focuses on the analysis and design of a resistorless sub-threshold voltage reference. A low power CMOS voltage reference is developed using 180 nm process technology. In conventional band gap reference bipolar transistors (BJT’s) and resistors are used, where BJT’s are parasitic in nature and resistors consume larger area on the silicon chip and therefore the cost of the chip will be increased. From conventional band gap reference, BJT’s and resistors are replaced with MOS transistors which operate in linear region and sub-threshold region respectively to generate the required proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) voltages. The proposed voltage reference circuit generates a stable voltage of 414.96 mV at 270C under 1.8 V of power supply. This circuit operates stable in the temperature range of –200C to 1200 C. Silicon chip area is 0.000916 mm2 and power consumption is 0.0016 µW. When the proposed work is compared with similar architectures 88% of reduction in chip area and 79% of reduction in power consumption is observed. These are the two important observed outcomes from this proposed work.

A Design of Low Power Resistorless Sub-threshold CMOS Bandgap Voltage Reference

Voltage references are very essential components of analog VLSI circuits A reference source is expected to remain constant against supply voltage, temperature and process parameter variations The forward voltage drop across junction diode exhibits a negative temperature dependence of about 2mV/°C, which is compensated by a suitably scaled proportional to absolute temperature (PTAT) component to obtain the bandgap voltage reference The conventional bandgap voltage reference constituting of bipolar transistors and opamp will consume more power and area In order to overcome this drawback, we propose a novel design of low power bandgap voltage reference that substitutes sub-threshold MOS transistors in place of bipolar transistors and a regenerative bias circuit in place of opamp The circuit works on a supply of 1V (±10%) and within a temperature range of −40°C to 125°C The circuit is designed to give a constant voltage of 5463mV with a temperature coefficient of 144ppm/°C The proposed circuit occupies an area of 00094mm2 which is very less as compared to commonly used architectures The designed architecture is tested across all the process corners [SS, FF, TT, SNFP and FNSP] in 180nm technology using CADENCE tool (UMC180)

Prashant Khot

Papers

Design of area efficient and low power bandgap voltage reference using sub-threshold MOS transistors