A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.

A metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenches

The present disclosure provides an integrated circuit product including a plurality of standard cells, each standard cell of the plurality of standard cells being in abutment with at least one other standard cell of the plurality of standard cells, a continuous active region continuously extending across the plurality of standard cells, at least two active regions being separated by an intermediate diffusion break, wherein each standard cell comprises at least one PMOS device and at least one NMOS device, the at least one PMOS device being provided in and above the continuous active region and the at least one NMOS device being provided in and above the at least two active regions.

Standard cell layout and method of arranging a plurality of standard cells

A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR input is configured to receive a data input to the data-gated flip-flop. The data-gated flip-flop includes a first latch including a first latch data input and a first latch reset input, the first exclusive OR output being coupled to the first latch data input and the first latch reset input. The data-gated flip-flop includes a second latch having a data output, the data output coupled to the second exclusive OR input.

Low clock power data-gated flip-flop

Hybrid diffusion standard library cells for engineering change orders (ECO), and related systems and methods are disclosed The hybrid diffusion standard library cells may be fabricated with reduced costs because masks corresponding to fixed base layers remain constant across integrated circuit (IC) devices The hybrid diffusion standard library cell includes at least one transistor and multiple diffusion regions (102(1-4)), wherein a break region (104) separates at least two of the multiple diffusion regions The hybrid diffusion standard library cell includes one or more MEOL interconnects (106(1-19)) at fixed locations that are configured to connect transistors to a first metal layer One of the interconnects (106(17)) may be disposed in the break region Including the break region between multiple diffusion regions helps to limit the locations of the fixed MEOL interconnects, which limits possible locations for base level transistors and fixes the base layer design

Hybrid diffusion standard library cells, and related systems and methods

A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.

Standard cell architecture for reduced leakage current and improved decoupling capacitance

A CMOS device including a standard cell includes first and second transistors with a gate between the first and second transistors. One active region extends between the first and second transistors and under the gate. In a first configuration, when drains/sources of the first and second transistors on the sides of the gate carry the same signal, the drains/sources are connected together and to the gate. In a second configuration, when a source of the first transistor on a side of the gate is connected to a source voltage and a drain/source of the second transistor on the other side of the gate carries a signal, the source of the first transistor is connected to the gate. In a third configuration, when sources of the first and second transistors on the sides of the gate are connected to a source voltage, the gate floats.

Digital circuit design with semi-continuous diffusion standard cell

In one embodiment, a method for signal delay in a scan path comprises, in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage. The method also comprises, in a functional mode, disabling the delay devices.

Circuit techniques for efficient scan hold path design

Techniques for fixing hold violations using metal-programmable cells are described herein. In one embodiment, a system comprises a first flip-flop, a second flip-flop, and a data path between the first and second flip-flops. The system further comprises a metal-programmable cell connected to the data path, wherein the metal-programmable cell is programmed to implement at least one capacitor to add a capacitive load to the data path. The capacitive load adds delay to the data path that prevents a hold violation at one of the first and second flip-flops.

Low overhead hold-violation fixing solution using metal-programable cells

In certain aspects, a semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die also includes a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed from a first middle of line (MOL) metal layer, and a second gate contact electrically coupled to the second gate, wherein the second gate contact is formed from the first MOL metal layer. The semiconductor die further includes an interconnect formed from a second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, and at least a portion of the interconnect is underneath the power rail.

Qi Ye

Papers

Digital circuit design with semi-continuous diffusion standard cell

Circuit techniques for efficient scan hold path design

Low overhead hold-violation fixing solution using metal-programable cells

Power rail inbound middle of line (mol) routing

Low clock power data-gated flip-flop