Showing papers by "Qiang Zhou published in 2004"
23 May 2004
TL;DR: This work presents a layout correction and optimization algorithm called MOPC; it's a flexible and efficient core for the model-based OPC system and the OPE between the neighboring segments of the inside feature are both considered during the correction.
Abstract: As the development of VLSI technique, the critical dimension of IC has become smaller than the exposure wavelength. Due to the diffraction and interaction of optical waves, deformations between the image on wafer and the feature on layout are undeniable. This results in bad performance or even invalid circuits of the chips. OPC is critical compensation technique to correct the deformations on wafer images. This work presents a layout correction and optimization algorithm called MOPC; it's a flexible and efficient core for the model-based OPC system. Since we divide the target features into different types before correction, the OPE between the target features and the environment features and the OPE between the neighboring segments of the inside feature are both considered during the correction.
4 citations
23 May 2004
TL;DR: A new design flow named recursive mixed mode placement (RMMP) is presented in this paper to provide a solution of MMP with this circuit's variety of block configuration taken into account and improves the algorithm efficiency.
Abstract: Mixed mode placement (MMP) is characterized by a number of same-height standard cells mixed with scattering big blocks in a fixed die. The variety of size and number of blocks introduces challenges to existing algorithms in achieving reasonable solution quality and running time. A new design flow named recursive mixed mode placement (RMMP) is presented in this paper to provide a solution of MMP with this circuit's variety of block configuration taken into account. It starts from recursively partitioning circuits to form a tree of virtual blocks in the different condition of the size and number of blocks as well as the logical or physical hierarchy. Then it combines floorplan on block level and quadratic place (Q-place) on cell level to complete the global placement. Our approach takes advantage of combining floorplan and Q-place algorithms to fit the variety of circuit's components. The combined approach improves the algorithm efficiency and obtains satisfactory results of MMP in terms of wire length and running time on various industry and academia test cases.
4 citations