A method and structure for providing ESD protection for Silicon-On-Insulator (SOI) integrated circuits. The ESD protection circuit includes an electrically conductive pad and first conductor segment fabricated over an insulating layer. The first conductor segment connects the pad directly to a first node, without an intervening input resistor. A first diode is fabricated over the insulating layer and connected between the first node and a first voltage supply rail. Similarly, a second diode is fabricated over the insulating layer and connected between the first node and a second voltage supply rail. Ballast resistors can be included in series with each of the diodes. A cross power supply clamp, also fabricated over the insulating layer, is connected between the first and second voltage supply rails. The first node of the ESD protection circuit is coupled to the SOI integrated circuit to be protected. The ESD protection circuit can be fabricated on a minimum number of silicon islands to improve local thermal spreading. Improved ESD protection is provided to input, output, and I/O pins of an SOI integrated circuit, while promoting high speed signal transfer between these pins and the integrated circuit.

Method and structure for providing ESD protection for silicon on insulator integrated circuits

Electrostatic discharge (ESD) protection circuitry having a string of diode-connected field-effect transistors (FETs) connected between a bus and ground plane for triggering a shunt element, such as a large n-channel FET, connected between the same or a different bus and the ground plane. The bus or buses are diode-connected through the base-emitter junction of pnp transistors to signal pads, as well as to a positive voltage power supply. The string of FETs turns on when the pad-to-ground voltage, and thus the bus-to-ground voltage, exceeds a threshold characteristic of an ESD event. The string acts as a voltage divider to bring a node between two of the FETs up to a voltage that will activate an n-channel trigger FET, which is part of a resistive-load inverter. This drives another inverter that in turn drives the shunt FET. When the voltage is pulled back down below the threshold voltage, the shunt FET continues to shunt current to the ground plane for the duration of the ESD event.

Electrostatic discharge protection circuit with dynamic triggering

A distributed electrostatic discharge (ESD) protection circuit (210) is used in high frequency integrated circuit. A transmission line from an integrated circuit (IC) pad (212) or package pin couples a plurality of ESD elements (220-223). The ESD element (220-223), such as diodes, are distributed along the transmission line and coupled from the transmission line to ground or a power supply. The effective impedance of the transmission line and ESD elements (220-223) is defined to match the impedance of an external line. Distributed ESD protection circuit (210) provides a high frequency signal path that can be used well into the GHz frequency range and also provides effective ESD protection.

Distributed esd protection device for high speed integrated circuits

An apparatus and method for protecting semiconductor switching devices from damage due to electrostatic discharge is provided. The apparatus detects the occurrence of an ESD event, and turns the switching circuit to an operating state in which electrostatic charge is dissipated through the switching circuit. In embodiments of the invention, the switching circuit is a CMOS inverter circuit and the apparatus includes a PMOS transistor that upon occurrence of an ESD event couples an output of the inverter circuit to ground to discharge the electrostatic charge.

Electrostatic discharge protection circuit for protecting CMOS transistors on integrated circuit processes

Tungsten-titanium sputter targets of at least 95% theoretical density are provided with little or no β(Ti, W) phase constituent. Such targets will minimize troublesome particulate emissions during sputter coating conditions.

Method of producing tungsten-titanium sputter targets and targets produced thereby

An electrostatic discharge protection circuit without the use of a series resistor is described. MOSFET transistors with a turn-on voltage above the postive supply voltage but below the breakdown voltage are used. In one embodiment, parasitic bipolar transistors formed in conjunction with the MOSFETs are employed for further protection.

Quincy Say

Papers

Resistorless electrostatic discharge protection device for high speed integrated circuits