This paper addresses two significant proximity effects, well proximity and STI stress, as they relate to analog circuit design. Device performance is impacted by layout features located near, but not part of the device. This adds new complexities to analog design. In either case, bias points can shift by 20-30%, causing potentially catastrophic failures in circuits. We show, for the first time, that a MOSFET placed close to a well-edge creates a graded channel.

Implications of Proximity Effects for Analog Design

The design of an analog-to-digital converter or digital-to-analog converter is one of the most fascinating tasks in micro-electronics. In a converter the analog world with all its intricacies meets the realm of the formal digital abstraction. Both disciplines must be understood for an optimum conversion solution. In a converter also system challenges meet technology opportunities. Modern systems rely on analog-to-digital converters as an essential part of the complex chain to access the physical world. And processors need the ultimate performance of digital-to-analog converters to present the results of their complex algorithms. The same progress in CMOS technology that enables these VLSI digital systems creates new challenges for analog-to-digital converters: lower signal swings, less power and variability issues. Last but not least, the analog-to-digital converter must follow the cost reduction trend. These changing boundary conditions require micro-electronics engineers to consider their design choices for every new design. Analog-to-Digital Conversion discusses the different analog-to-digital conversion principles: sampling, quantization, reference generation, nyquist architectures and sigma-delta modulation. Analog-to-Digital Conversion presents an overview of the state-of-the-art in this field and focuses on issues of optimizing accuracy and speed while reducing the power level. A lot of background knowledge and practical tips complement the discussion of basic principles, which makes Analog-to-Digital Conversion also a reference for the experienced engineer.

Analog-to-Digital Conversion

This paper presents an electrical analysis of mechanical stress induced by shallow trench isolation (STI) on MOSFETs of advanced 0.13 /spl mu/m bulk and silicon-on-insulator (SOI) technologies. By applying external calibrated stress, we present piezoresistive coefficients measurements on these technologies, and we compare small and long transistors electrical responses, evidencing the strong effect of source drain resistance R/sub sd/. Then, using the same approach on short devices with different gate-edge-to-STI distances, we quantitatively evaluate stress profile induced by STI and its mean value under the gate of the devices. Results are discussed to explain differences between bulk and SOI technologies, as well as between nMOS and pMOS. We show that the observed higher pMOS drain current shift is related to the process, and may be explained by doping amorphization and recrystallization effects, and not by a piezoresistive coefficient difference as usually assumed.

Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress

Variation in transistor characteristics is increasing as CMOS transistors are scaled to nanometer feature sizes. This increase in transistor variability poses a serious challenge to the cost-effective utilization of scaled technologies. Meeting this challenge requires comprehensive and efficient approaches for variability characterization, minimization, and mitigation. This paper describes an efficient infrastructure for characterizing the various types of variation in transistor characteristics. A sample of results obtained from applying this infrastructure to a number of technologies at the 90-, 65-, and 45-nm nodes is presented. This paper then illustrates the impact of the observed variability on SRAM, analog and digital circuit blocks used in system-on-chip designs. Different approaches for minimizing transistor variation and mitigating its impact on product performance and yield are also described.

Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies

A test-chip in a low-power 45 nm technology, featuring uniaxial strained-Si, has been built to study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D), wafer-to-wafer (W2W) and within-die (WID) variability has been measured over multiple wafers, analyzed and attributed to likely causes in the manufacturing process. Delay is characterized using an array of ring oscillators and transistor leakage current is measured with an on-chip ADC. The key results link systematic layout-dependent and die-to-die variability as being caused by gate patterning and material strain. In comparison to a previous 90 nm experiment, gate proximity now contributes less to frequency variability, causing a 2% change in overall performance, while strain has increased its contribution to about 5% of the overall performance.

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Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology

A new approach is presented aimed at modeling mechanical stress effects which impact MOSFET electrical behavior. It is successful in accounting for mobility variations experimentally evidenced on complex MOSFET geometries. The newly developed mobility model proves to be an efficient way to include mechanical stress effects into standard simulation models. We show that stress effects can and should be taken into account in the IC design phase in present and sub 90 nm nodes CMOS generations.

R. A. Bianchi

Papers

Accurate Modeling of Trench Isolation Induced Mechanical Stress effects on MOSFET Electrical Performance