Showing papers by "R.D. Blanton published in 2003"

Analyzing the effectiveness of multiple-detect test sets

Abstract: Multiple-detect test sets have been shown to be effective in lowering defect level. Other researchers have noted that observing the effects of a defect can be controlled by sensitizing affected sites to circuit outputs but defect excitation is inherently probabilistic given a defect’s inherent, unknown nature. As a result, test sets that sensitize every signal line multiple times with varying circuit state has a greater probability of detecting a defect. In past work, the entire circuit is considered when varying circuit state from one vector to another for a given signal line. However, it may be possible to improve defect excitation by exploiting the localized nature of many defect types. Spec$cally, by varying circuit state in the physical region or neighborhood surrounding a line affected by a defect, the defect excitation and therefore detection can be improved. In this paper, we present a method for extracting a physical region surrounding a signal line but more importantly, techniques for analyzing the excitation characteristics of the region. Analysis of 4-detect test sets reveals that 30% to 60% of signal line regions do not achieve at least four unique states, indicating opportunity to further reduce defect level.

On the properties of the input pattern fault model

Abstract: A review of traditional IC failure analysis techniques strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard single stuck-line- (SSL-) based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting nontargeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

Deformations of ic structure in test and yield learning

Abstract: This paper argues that the existing approaches to modelingand characterization of IC malfunctions are inadequate fortest and yield learning of Deep Sub-Micron (DSM) products.Traditional notions of a spot defect and local and global pro-cess variations are analyzed and their shortcomings areexposed. A detailed taxonomy of process-induced deforma-tions of DSM IC structures, enabling modeling and charac-terization of IC malfunctions, is proposed. The blueprint of aroadmap enabling such a characterization is suggested. Keywords : yield learning, fault modeling, defects, diagno-sis, defect characterization. 1 Introduction The motivation, purpose and overall structure of this paperhave already been explained in the abstract above. The dis-cussion of the prior and relevant publications should be thenext natural component of this paper. But it is skipped aswell, even if there exists substantial body of relevant publi-cations in the related domain (some of them are listed as ref-erences in [1,2].) It is skipped to avoid unnecessarydiscussion of the weaknesses of related results presented inthe past. Simply, majority of published papers with the ICtechnology-oriented flavour (and prime examples are the fol-lowing papers co-written by the first author of this paper [3,4, 5, 6, 7, 8]) do not offer sufficient insight into failure mech-anisms to address challenges posed by the DSM era prod-ucts. A substantial portion of this paper attempts to justify theabove, somewhat provocative claim. Then the remainingportion of the paper is used to suggest directions of theresearch, which we should undertake to truly assist test andyield learning of modern era ICs.

Built-in self test of MEMS

Abstract: The present disclosure is directed to an apparatus and method for producing and comparing signals from various points in a MEMS device. By producing signals which should be of substantial identical characteristics, deviations from the situation where the signals are of identical characteristics can be used to identify various types of asymmetry which are otherwise difficult to detect. In one embodiment, the MEMS device is comprised of a plurality of fixed beams arranged symmetrically and a plurality of movable beams arranged symmetrically. A first sensor is formed by certain of the fixed and movable beams while a second sensor, electrically isolated from said first sensor, is formed by at least certain other of the fixed and movable beams. The first and second sensors are located within the MEMS device so as to produce signals of substantially identical characteristics. A circuit is responsive to the first and second sensors for comparing the signals produced by the first and second sensors. In addition to the apparatus, methods of performing a self test are also disclosed, which may be performed in real time.

Progressive bridge identification

Abstract: We present an efficient algorithm for identification of two-line bridges in combinational CMOS logic that narrows down the two-line bridge candidates based on tester responses for voltage tests. Due to the implicit enumeration of bridge sites, no layout extraction or precomputed stuck-at fault dictionaries are required. The bridge identification is easily refined using additional test pattern results when necessary. We present results for benchmark circuits and four common fault models (wiredAND, wired-OR, dominant, and composite), evaluate the diagnosis against other possible fault types, and summarize the quality of our results.

Path delay test generation for domino logic circuits in the presence of crosstalk

Abstract: A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of a domino gate in the presence of crosstalk is developed and exploited by a new efJicient timing analysis algorithm. The algorithm uses a single, breadth-jirst traversal to compute delays in the presence of crosstalk. Thus, it avoids the iterative methods commonly employed for static CMOS circuits. The timing analysis technique is used to generate test input vectors that exercise the worst-case delays of a multiplier circuit implemented using domino logic. Hspice simulation results demonstrate that the technique identiJes test vectors that produce circuit delay that satisfy the targeted value in the presence of crosstalk.

ATPG for Noise-Induced Switch Failures in Domino Logic

Abstract: Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with technology scaling, domino circuits are increasingly susceptible to switch failures due to various noise sources that include crosstalk, charge sharing and leakage. To test for such failures in a manufactured chip, we describe a test pattern generation methodology that generates specific test patterns to target such failures. These test patterns activate noise from multiple sources such that their combined effect causes a switch failure at a domino gate output. In addition, the test patterns propagate the resulting error to an observable output within the duration of the circuit's clock cycle. The methodology has been implemented and validated using a domino multiplier circuit.