Showing papers by "R.D. Blanton published in 2022"

Secuirty Metrics for Logic Circuits

Abstract: Any type of engineered design requires metrics for trading off both desirable and undesirable properties. For integrated circuits, typical properties include circuit size, performance, power, etc., where for example, performance is a desirable property and power consumption is not. Security metrics, on the other hand, are extremely difficult to develop because there are active adversaries that intend to compromise the protected circuitry. This implies metric values may not be static quantities, but instead are measures that degrade depending on attack effectiveness. In order to deal with this dynamic aspect of a security metric, a general attack model is proposed that enables the effectiveness of various security approaches to be directly compared in the context of an attack. Here, we describe, define and demonstrate that the metrics presented are both meaningful and measurable.

Large-Scale Logic-Locking Attacks via Simulation

Abstract: Because IC security has become an increasingly prevalent issue for hardware designers, a number of IC protection schemes have been introduced in the literature. One such scheme, logic locking, involves transforming a hardware design so that it will not operate correctly unless extra inputs (called key inputs) are driven to specific values that are secret. Many existing logic-locking solutions are vulnerable to attacks that uncover the key-input values necessary for correct operation. However, the success of such attacks wane as the size of the design and the number of key inputs increases. In this work, we introduce a logic-locking attack which uses circuit simulators to determine key-input values from large-scale circuits with thousands of added key inputs. Attacks performed on such designs demonstrate the effectiveness of this approach in comparison to other attacks.

Testability Properties of Divergent Trees Testability Properties of Divergent Trees

Abstract: . The testability of a class of regular circuits called divergent trees is investigated under a functional fault model. Divergent trees include such practical circuits as decoders and demultiplexers. We prove that uncontrolled divergent trees are testable with a fixed number of test patterns (C-testable) if and only if the module function is surjective. Testable controlled trees are also surjective but require sensitizing vectors for error propagation. We derive the conditions for testing controlled divergent trees with a test set whose size is proportional to the number of levels p found in the tree (L-testability). By viewing a tree as overlapping arrays of various types, we also derive conditions for a controlled divergent tree to be C-testable. Typical decoders/demultiplexers are shown to only partially satisfy L- and C-testability conditions but a design modification that ensures L-testability is demonstrated.

Efficient Test Chip Design via Smart Computation

Abstract: Submitted to the Special Issue on Machine Learning for CAD (ML-CAD). Competitive strength in semiconductor field depends on yield. The challenges associated with designing and manufacturing of leading-edge integrated circuits (ICs) have increased that reduce yield. Test chips, especially full-flow logic test chips, are increasingly employed to investigate the complex interaction between layout features and the process that improves the total process quality before and during initial mass production. However, designing a high-quality full-flow logic test chip can be time-consuming due to the huge design space and complex process to search for optimal result. This work describes a new design flow that significantly accelerates the logic test chip design process. First, we deploy random forest classification technique to predict potential synthesis outcome for test chip design exploration. Next, a new method is described to efficiently solve the integer programming problem involved in the design process. Various experiments with industrial design have demonstrated that the proposed two methods greatly improve the design efficiency.

PEPR: Pseudo-Exhaustive Physically-Aware Region Testing

Abstract: Recent reports indicate that existing fault models and test metrics result in substantial manufacturing test escapes that cause major system-level challenges such as silent data corruption resulting from incorrect computations. Such test escapes are often detected today after system deployment (e.g., in the field) using a variety of synthetic and application workloads. In this work, a new test metric is investigated for detecting defects that escape existing test approaches. PEPR (Pseudo-Exhaustive Physically-Aware Region) testing comprehensively analyzes both the physical layout and the logic netlist to identify single- or multi- output sub-circuits. The resulting sub-circuits are exhaustively tested to detect timing-independent combinational (TIC) defects. Analyses demonstrate that PEPR-based scan tests detect TIC defects perfectly (100%) when examining fail data from over 30,000 14nm failing chips. In contrast, existing fault models and test metrics might result in up to 95 % of TIC defects being detected fortuitously. Strategies for addressing increased test pattern count resulting from the pseudo-exhaustive nature of PEPR testing are also discussed.