Impact life prediction modeling of TFBGA packages under board level drop test

TSV interposer has emerged as a good solution to provide high wiring density interconnections, improved electrical performance due to shorter interconnection from the die to substrate, and minimized CTE mismatch between the chip and copper filled TSV interposer, resulting in high reliability micro bumps and more reliable low-k chip Furthermore, for an interposer that does not contain any active device, already established process technology could be applied, TSV pitch could be coarser and a thicker interposer could be used This paper presents the development of TSV interposer technology for a high-performance 28nm logic die that is mounted on a large silicon interposer with Cu through silicon via A representative silicon interposer test chip with thousands of micro-bumps at 45um pitch has been fabricated The silicon interposer is 100um thick, and is mounted on a 425mm×425mm substrate through 180um pitch C4 bumps TSV fabrication process steps and assembly process of the large logic die mounted on the TSV interposer with lead-free micro-bumps have been optimized as well as assembly of the component on the organic substrate 3D thermal-mechanical modeling and simulation for the packaged device with TSV interposer have been performed The samples have been subjected to thermal cycling, electro-migration and moisture sensitivity tests Effect of TSV interposer on the stress of the die, low-k layers and fatigue life of micro bumps and C4 bumps have been investigated Several DOEs have been performed to optimize design and material selection in order to maximize yield and reliability Finally, Si interposer seemed to be a low-risk 3D path to have a reliable package with acceptable warpage/coplanarity, passing 1000TCB without any crack, delamination or void being detected in low-k, TSV, micro bumps and C4 bumps

Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA

The reliability concern in flip-chip-on-board (FCOB) technology is the high thermal mismatch deformation between the silicon die and the printed circuit board that results in large solder joint stresses and strains causing fatigue failure. Accelerated thermal cycling (ATC) test is one of the reliability tests performed to evaluate the fatigue strength of the solder interconnects. Finite element analysis (FEA) was employed to simulate thermal cycling loading for solder joint reliability in electronic assemblies. This study investigates different methods of implementing thermal cycling analysis, namely using the "dwell creep" and "full creep" methods based on a phenomenological approach to modeling time independent plastic and time dependent creep deformations. There are significant differences between the "dwell creep" and "full creep" analysis results for the flip chip solder joint strain responses and the predicted fatigue life. Comparison was made with a rate dependent viscoplastic analysis approach. Investigations on thermal cycling analysis of the temperature range, (/spl Delta/T) effects on the predicted fatigue lives of solder joints are reported.

Thermal cycling analysis of flip-chip solder joint reliability

Fine-pitch ball grid array (BGA) and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in automotive underhood environment is not well understood. In this work, the reliability of fine-pitch plastic ball grid array (PBGA) packages has been evaluated in the automotive underhood environment. Experimental studies indicate that the coefficient of thermal expansion (CTE) as measured by thermomechanical analyzer (TMA) typically starts to change at 10-15/spl deg/C lower temperature than the T/sub g/ specified by differential scanning calorimetry (DSC) potentially extending the change in CTE well into the accelerated test envelope in the neighborhood of 125/spl deg/C. High T/sub g/ substrates with glass-transition temperatures much higher than the 125/spl deg/C high temperature limit, are therefore not subject to the effect of high coefficient of thermal expansion close to the high temperature of the accelerated test. Darveaux's damage relationships were derived on ceramic ball grid array (CBGA) assemblies, with predominantly solder mask defined (SMD) pads and 62Sn36Pb2Ag solder. In addition to significant differences in the crack propagation paths for the two pad constructions, SMD pads fail significantly faster than the non solder mask defined (NSMD) pads in thermal fatigue. The thermal mismatch on CBGAs is much larger than PBGA assemblies. Crack propagation in CBGAs is often observed predominantly on the package side as opposed to both package and board side for PBGAs. In the present study, crack propagation data has been acquired on assemblies with 15, 17, and 23mm size plastic BGAs with NSMD pads and 63Sn37Pb on high-T/sub g/ printed circuit boards. The data has been benchmarked against Darveaux's data on CBGA assemblies. Experimental matrix also encompasses the effect of bis-maleimide triazine (BT) substrate thickness on reliability. Damage constants have been developed and compared against existing Darveaux Constants. Prediction error has been quantified for both sets of constants.

Model for BGA and CSP reliability in automotive underhood applications

Reliabilit!- perfonnance of IC packages during drop impact is critical, especially for handheld electronic products. Currently. thcrc is no detailed test standard in the industry to advise on the procedures for board level dmp test. nor there is any model Ilia1 providcs good correlation with experimental ineasiircinents of acceleration and impact life. In this paper; detailed drop tests and simulations are pcrfonned on TFBGA (Thin-profile Fine-pitch BGA) and VFBGA (Vey-thinprofile Fine-pitch BGA) packages at board level using testing procediires developed in-house. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and iueclwnical shock during impact. The critical solder ball is obsewed to occur at the outennost comer solder .joint_ and fails along the solder and PCB pad interface. Various testing parameters are studied experimentally and analytically. to understand the effects of drop heightl drop oricntation, number of PCB mounting screws to fixture. position of component on board: PCB bending: solder material, and etc. Drop height, fclt thickness, and contact conditions are used to fine-tune the shape aud level of shock pulse required. Board level drop test can be better controlled. compared with system or product level test such as impact of mobile phone. which sometimes has rather unpredictable results due to higher complexity and variations in drop orientation. At tlie same time, dynamic simulation is perfonncd to compare with esperiniental results. The model established has close values of peak acceleration and impact duration as measured in actual drop test. The failure mode and critical solder ball location predicted by modeling correlate well with testing. For the first time, an accurate life prediction model is proposed for board level drop test to estiinatc the number of drops to failure for a package. For the correlation cases studied. the nminmm nonual peeling stresses of critical solder joints correlate well with the mean impact lives measured during the drop test. The uncertainty of impact life prediction is within M drops, for a typical test of 50 drops. With this new model, a failure-free state can be detennined, and drop test performance of new package design can be quantified. and fuliher enhanced through modeling. This quantitative approach is different from traditional qualitative modeling. as it provides both accurate relative and absolute impact life prediction. The relative performance of package may be different under board level drop test ,and thennal cycling test. Different design guidelines should be considered, depcnding on application and area of concern

Board level drop test and simulation of TFBGA packages for telecommunication applications

A generalized solder joint fatigue life model for surface mount packages was previously published by the author. The model is based on correlation to measured crack growth data on BGA joints during thermal cycling. It was subsequently discovered by Anderson et. al. that the ANSYS/sup TM/ 5.2 finite element code used in the model had an error in its method for calculating plastic work. It was shown that significant error in life prediction could result by using a recent version of the code where the bug has been fixed. The error comes about since the original crack growth constants were derived based on plastic work calculations that had the bug. In this paper, crack initiation and growth constants are recalculated using ANSYS/sup TM/ 5.6. In addition, several other model related issues are explored with respect to the crack growth correlations. For example, 3D slice models were compared to quarter symmetry models. Anand's constitutive model was compared with Darveaux's constitutive model. It was shown that the crack growth rate dependence on strain energy density always had an exponent of 1.10+/-0.15. This is in the range of the original correlation, so the accuracy of relative predictions should still be within+/-25%. However, the accuracy of absolute predictions could be off by a factor of 7 in the worst case, if the analyst uses a modeling procedure that is not consistent with that used for the crack growth correlation. The key to good accuracy is to maintain consistency in the modeling procedure.

R. Darveaux

Papers

Effect of simulation methodology on solder joint crack growth correlation