Contemporary hardware implementations of artificial neural networks face the burden of excess area requirement due to resource-intensive elements such as multiplier and non-linear activation functions. The present work addresses this challenge by proposing a resource-efficient Co-ordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) which can be configured to compute both multiply-accumulate (MAC) and non-linear activation function (AF) operations. The CORDIC-based architecture uses linear and trigonometric relationships to realize MAC and AF operations respectively. The proposed design is synthesized and verified at 45nm technology using Cadence Virtuoso for all physical parameters. Implementation of the signed fixed-point 8-bit MAC using our design, shows 60% less area, latency, and power product (ALP) and shows improvement by 38% in area, 27% in power dissipation, and 15% in latency with respect to the state-of-the-art MAC design. Further, Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that worst-case mean is $189.73\mu W$ which is 63% of the state-of-the-art.

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RECON: Resource-Efficient CORDIC-Based Neuron Architecture

Online arithmetic operators offer advantages of reduction in resource utilization and interconnection complexity besides providing pipelining at digit level. Multiplierless constant coefficient multiplication using the shift-and-add technique is widely used in digital signal processing applications. This paper proposes a novel bit serial adaptation of the parallel shift-and-add algorithm to online arithmetic. The proposed multipliers use right shifts instead of the traditional left shifts resulting in causal online implementations. Graph-based and hybrid algorithms are developed for the estimation of the distance of a constant from a set of constants in terms of the number of additions and for the synthesis of online multiple constant multipliers under area and online delay constraints. The computational complexity of the algorithms is determined. Results of implementation on randomly generated constant sets and FIR filter instances show substantial improvements in the number of operations required using the distance heuristic. Further, it is shown that the proposed techniques and algorithms result in significant savings in resource utilization, logic depth, and clock frequency compared to parallel and digit-serial algorithms.

Algorithms for Multiplierless Multiple Constant Multiplication in Online Arithmetic

Single and Multiple constant multiplications are key operations in several digital signal processing algorithms. This paper develops a mathematical framework for a novel adaptation of the parallel shift-and-add multiplication algorithm for online arithmetic. Based on this adaptation, online constant coefficient multipliers for single constant multiplication (SCM) and multiple constant multiplications (MCM) of streaming floating-point inputs are presented. A finite impulse response filter implementation on Xilinx Virtex 6 Field programmable gate array (FPGA) is used as an example to illustrate the merits of these filters. The results of this implementation show that online multipliers reduce resource utilization, online delay and increase clock frequency in comparison to existing designs. Online multiple constant multipliers also show an average  reduction of 65% in the number of slice LUTs and 37%  in the number of slice registers required when compared to existing digit-serial multiple constant multipliers. Thus, the proposed online arithmetic operators appear to be good alternatives for constant coefficient multiplication

A Mathematical Framework for Online Constant Coefficient Multiplication

In our recent work on iterative computation in hardware, we showed that arbitrary-precision solvers can perform more favorably than their traditional arithmetic equivalents when the latter’s precisions are either under- or over-budgeted for the solution of the problem at hand. Significant proportions of these performance improvements stem from the ability to infer the existence of identical most-significant digits between iterations. This technique uses properties of algorithms operating on redundantly represented numbers to allow the generation of those digits to be skipped, increasing efficiency. It is unable, however, to guarantee that digits will stabilize, i.e., never change in any future iteration. In this article, we address this shortcoming, using interval and forward error analyses to prove that digits of high significance will become stable when computing the approximants of systems of linear equations using stationary iterative methods. We formalize the relationship between matrix conditioning and the rate of growth in most-significant digit stability, using this information to converge to our desired results more quickly. Versus our previous work, an exemplary hardware realization of this new technique achieves an up-to 2.2× speedup in the solution of a set of variously conditioned systems using the Jacobi method.

Digit Stability Inference for Iterative Methods Using Redundant Number Representation

The transpose form of (FIR) is a pipeline structure that supports the MCM (Multiple Constant Multiplication) technology, but the direct form of the FIR filter shape is not compatible with the MCM technique. MCM is most effective for the transpose form when the overall operation is greater than the regular additions that reduce computation delays. In this paper, efficient Pipeline based FIR filter with MCM designed was implemented using Verilog HDL, simulated, synthesized in Xilinx ISE tool, and implemented on ARTIX-7 FPGA board. Results shows that area, delay and computational complexity reduced for MCM based FIR filter with pipeline comparative to without pipeline.

FPGA Implementation of FIR Filter Architecture using MCM Technology with Pipelining

Digital signal processing hardware uses digit serial arithmetic when latency can be traded off for higher clock speeds, resource and input-output utilization. Floating-point representations are important when dealing with very large data sets or sets where data range may be unpredictable as these representations may have a larger dynamic range. Field Programmable Gate Array architectures make them suitable as hardware accelerators for implementing high performance floating-point computations. In this paper, a number of improved designs for Radix-2h online floating-point multiplication are presented, analysed and compared on the basis of latency, throughput, cycle time and resource utilization. The architecture of a novel online floating-point multiplier using an interleaved number representation that results in an increased throughput and has the advantage of carrying out normalization for overflow with reduction in cycle time, resource utilization and latency is also presented.

Radix-2 h online floating point multipliers

Online arithmetic implementation of digital signal processing hardware improves clock frequency and reduces in-put/output utilization, area and power at the cost of higher latency. Online constant coefficient multiplication requires adaptation of the conventional shift-and-add algorithm to make the implementation non-causal. This paper presents algorithms for computing key metrics for evaluating solutions of online multiple constant multi-plication (OMCM) problems – online delay and number of flipflops. As the OMCM problem is NP-complete, these metrics can also be used as constraints to obtain solutions to the OMCM prob-lem in polynomial time. Analysis of the impact of imposing online delay constraints shows reduction in maximum online delay at the expense of an increase in the number of adders required.

R. Devanathan

Papers

Algorithms for Multiplierless Multiple Constant Multiplication in Online Arithmetic

A Mathematical Framework for Online Constant Coefficient Multiplication

Radix-2 h online floating point multipliers

Computation of Design Metrics in Online Arithmetic Networks