Standard process CMOS/SOS technology has been applied in the design of a 6 bit parallel 20 MHz A/D converter. Two chips may be interconnected in a series to obtain 7 bit resolution or in parallel to obtain nearly 40 MHz data rates. Design factors and accuracy requirements are reviewed.

Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ICs. >

The design of radiation-hardened ICs for space: a compendium of approaches

In a static RAM fully asynchronous active equilibration and pre-charging of the RAM's bit lines (24) provides improved memory access time and lower active power dissipation. Each change in the memory's row (34) address is sensed for developing a clock pulse (50) of a controlled duration. The clock pulse (50) is received by a group of equilibrating transistors (46) and a group of pre-charging transistors (46) which are coupled to the memory's bit lines. When the clock pulse (50) occurs, all the above-mentioned transistors (46) conduct to effect simultaneous equilibration and pre-charging of the bit lines (24).

Asynchronously equilibrated and pre-charged static ram

A single bitline cross-point cell activation (SCPA) architecture that reduces active power consumption and reduces the chip size of high-density SRAMs (static random access memories) is presented. The architecture enables the smallest column current possible without increasing the block division of the cell array. Since the decoder area is reduced due to less block division, the memory core can be smaller than with a conventional divided word line (DWL) structure. In the SCPA, the total active current is 15.9 mA, while in the conventional architecture it is 26.1 mA. In the SCPA, the memory cell size is equal to that in the conventional architecture; however, the number of local decoders is reduced from 64 to 8. Moreover, the number of GND lines is reduced because of a much smaller column current in SCPA. As a result, the area of the memory core is reduced by 10% in a 16-Mb SRAM. >

A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's

A dual port memory is implemented in complementary (e.g., CMOS) technology so as to allow simultaneous uncontested read operations to the same memory cell. This is achieved by accessing one node of a bistable static cell through a n-channel and a p-channel access transistor. The opposite node is typically left unconnected to external access means. This technique also reduces the area required to implement the memory cell as compared to prior art NMOS techniques. If desired, an arbitration circuit can be included to arbitrate between simultaneous read/read or read/write operations on the same cell from the two ports.

Dual port complementary memory

A new CMOS/SOS `buried-contact' process allows fabrication of dense static memory cells. The technology is applied in a 16K RAM with 1150 /spl mu/m/SUP 2/ (1.78 mil/SUP 2/) cells based on 5 /spl mu/m design rules.

R.G. Stewart

Papers

16K CMOS/SOS asynchronous static RAM