ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.

Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI

ESD protection for RF applications must deal with good ESD performance, minimum capacitance, zero series resistance and good capacitance linearity. In order to fulfil these requirements, different ESD protection strategies for RF applications have been investigated in a 0.18 /spl mu/m CMOS process. This paper compares different ESD protection devices and shows that a suitable ESD performance target for RF applications (200 fF max, 2 kV HBM) can be reached with a diode network scheme. The optimization of the diodes is then a key point which is detailed. A trade-off must be found between the ESD performance, the voltage drop during ESD and the parasitic capacitance. Poly as well as STI bounded diodes have been studied and it appears clearly that a solution based on poly bounded diodes is the best choice.

Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 /spl mu/m CMOS process

A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

Large PMOS FETs with multiple gates can be arranged to provide ESD protection to high voltage on-chip power supplies in submicron CMOS integrated circuits. These clamps divide the supply voltage among several gate oxides; the circuitry accompanying the large series FETs provides near-maximum gate drive during ESD for high pulsed current. Layouts are densely packed because minimum dimensions can be used and because no contact is needed between the stacked gates. The high voltage designs are extensions of the large PMOS FET ESD clamps and timed drive circuitry that are used to clamp ordinary on-chip power supply lines.

Stacked PMOS clamps for high voltage power supply protection

Because of leakage problems related to avalanche breakdown of salicided junctions, an array of ESD protection methods has been developed and tested which depend on forward biased diodes and normal MOSFET conduction. These methods include the case of multiple power supplies, the case where the pad voltage can exceed the power supply voltage, and the case where the pad voltage both exceeds the power supply voltage and the process voltage limit. These methods result in parts made in 0.8 and 0.6 /spl mu/m salicided technologies routinely passing our upper division spec. of /spl plusmn/4500 V HBM without any discernible increase in pin leakage. Also, split supply salicided parts pass 1 kV of CDM with no discernible pin leakage increase and 2 kV with pin leakage increase but within spec. (10 /spl mu/A).

R. Gupta

Papers

Sub-micron chip ESD protection schemes which avoid avalanching junctions