This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentary nature among various LDMOS/DeMOS devices are shown. Based on the physical understanding, device optimization guidelines are given. Finally, an outlook on technology scaling is presented.

A Review on the ESD Robustness of Drain-Extended MOS Devices

Conductivity Modulation in Semiconductor Structures Under Breakdown and Injection.- Standard and ESD Devices in Integrated Process Technologies.- ESD Clamps.- ESD Network Design Principles.- ESD Design for Signal Path Analog.- Power Management Circuits' ESD Protection.- System-Level and Discrete Components ESD.

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ESD Design for Analog Circuits

Established methods for testing ESD robustness of high-voltage pins in smart power CMOS can lead to erroneous results. This paper investigates both LDNMOS and certain types of SCRLDMOS (SCRs embedded in LDNMOS) high-voltage clamps for safe-operating-area collapse due to trigger voltage (V t1) walk-in after transmission-line pulsing (TLP) corresponding to leakage-current increase below I t2. For the first time, the evolution of V t1 as a function of the number of TLP pulses and their magnitude is shown. Furthermore, some high-voltage clamps that are robust on their own are shown to walk-in in certain circuit environments that present high capacitance. The physical mechanism for this leakage enhancement and trigger-voltage walk-in has been established through failure analysis to be consistent with melt filament growth perhaps aided by metal migration. A simple phenomenological model is proposed to explain this behavior. Finally, the ability to avoid such V t1 collapse in SCRLDMOS through simple layout changes is shown.

High-Voltage CMOS ESD and the Safe Operating Area

An electrostatic discharge (ESD) protection design for smart power applications with lateral double-diffused MOS (LDMOS) transistors is investigated. With the gate-driven and substrate-triggered circuit techniques, the n-channel LDMOS can be quickly turned on to protect the output drivers during an ESD stress event. The proposed gate-driven and substrate-triggered ESD protection circuits have been successfully verified in a 0.35-μm 5 V/40 V bipolar CMOS DMOS (BCD) process, which can sustain ESD voltages of 4 kV in human-body-model (HBM) and 275 V in machine-model (MM) ESD tests. In addition, the power-rail ESD protection design can also be achieved with a stacked structure to protect 40-V power pins without a latchup issue in the smart power integrated circuits.

https://ir.nctu.edu.tw:443/bitstream/11536/26301/1/000284417700022.pdf

ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology

LDMOS transistors are widely used as output drivers in multiple applications in smart power IC designs. Relative to their sizes, LDMOS transistors are inherently weak with respect to ESD reliability and enhancing their ESD robustness has been an on-going challenge for many years. Snapback breakdown in MOSFET devices has been widely employed to explain the device failures due to ESD. A figure depicts a typical I-V characteristic and the testing device leakage evolution for a MOSFET device subject to transmission-line-pulse (TLP) ESD stress. For most conventional MOSFET devices, the first snapback breakdown, defined It1 and Vt1, is not a threat to the device until it reaches its thermal limit, It2. For most LDMOS cases, however, the first snapback breakdown can lead to the device damage. It has been broadly accepted that non-uniform snapback breakdown leads to current filamentation/crowding, which leads to excessive heating and failure. For a given type of LDMOS, two different failure modes are observed, which is dependent upon the effective gate width. A description and explanation of the different failure mechanisms due to these effects on the devices with different geometry is provided

Snapback Breakdown Dynamics and ESD Susceptibility of LDMOS

Lateral DMOS (LDMOS) power transistors of SMART technologies are widely used as output drivers in multiple applications. However, LDMOS devices are generally not robust under ESD due to deep snapback causing localized current crowding and leading to inhomogeneous triggering of the parasitic bipolar, ESD ruggedness of LDMOS power devices has been a significant subject in smart power IC technology. Lack of understanding in geometry scalability of the LDMOS devices often thwarts a proper implementation of self-protected structures. Therefore, it is necessary to understand the ESD scalability and failure mechanism of the power output devices to meet various levels of design requirement and optimize ESD protection solution. LDMOS devices ESD capability has been understood from snapback breakdown of the parasitic bipolar components. They usually show different behavior under ESD stress conditions, compared to the normal MOS transistors. The triggering mechanism of the snapback breakdown has been major subjects in terms of device structures and designs. In this paper, we report an ESD capability and scalability of the LDMOS devices from the geometry and operational aspects, employing both experimental and simulation data. Difference of transient electrical behaviors and failure mechanisms of DMOS with different geometries under ESD stress conditions is also addressed

ESD Scalability of LDMOS Devices for Self-Protected Output Drivers

Energy capability and electrostatic discharge characteristics of an LDMOS device exhibit a strong dependence on both active area and geometry of the device. It results from coupling processes between electrical and thermal entities within various components in the structure. This paper deals with energy and ESD ruggedness details of LDMOS devices in terms of device geometry using experimental and simulation results.

R. Ida

Papers

Snapback Breakdown Dynamics and ESD Susceptibility of LDMOS

ESD Scalability of LDMOS Devices for Self-Protected Output Drivers

Geometry effect on power and ESD capability of LDMOS power devices