The impact of statistical dopant fluctuations on the threshold voltage V/sub T/ and device performance of silicon MOSFET's is investigated by means of analytical and numerical modeling. A new analytical model describing dopant fluctuations in the active device area enables the derivation of the standard deviation, /spl sigma/V/sub T/, of the threshold voltage distribution for arbitrary channel doping profiles. Using the MINIMOS device simulator to extend the analytical approach, it is found that /spl sigma/V/sub T/, can be properly derived from two-dimensional (2-D) or three-dimensional (3-D) simulations using a relatively coarse simulation grid. Evaluating the threshold voltage shift arising from dopant fluctuations, on the other hand, calls for full 3-D simulations with a numerical grid that is sufficiently refined to represent the discrete nature of the dopant distribution. The average V/sub T/-shift is found to be positive for long, narrow devices, and negative for short, wide devices. The fast 2-D MINIMOS modeling of dopant fluctuations enables an extensive statistical analysis of the intrinsic spreading in a large set of compact model parameters for state-of-the-art CMOS technology. It is predicted that V/sub T/-variations due to dopant fluctuations become unacceptably large in CMOS generations of 0.18 /spl mu/m and beyond when the present scaling scenarios are pursued. Parameter variations can be drastically reduced by using alternative device designs with ground-plane channel profiles.

Modeling statistical dopant fluctuations in MOS transistors

An analytical model for circuit simulation to describe the channel thermal noise in MOSFET's for all channel length down to deep submicron is presented and verified by measurements. Contrary to the thermal equilibrium assumption, this model includes the influence of the increasing electrical field with downscaling on the channel carrier (electron, hole) equivalent noise temperature. If not taken into account, simulation errors of up to 100% and more in the thermal noise of half micron transistors and below occur.

An analytical thermal noise model of deep submicron MOSFET's

Transconductors are commonly used as active elements in high-frequency (HF) filters, amplifiers, mixers, and oscillators. This paper reviews transconductor design by focusing on the V-I kernel that determines the key transconductor properties. Based on bandwidth considerations, simple V-I kernels with few or no internal nodes are preferred. In a systematic way, virtually all simple kernels published in literature are generated. This is done in two steps: 1) basic 3-terminal transconductors are covered and 2) then five different techniques to combine two of them in a composite V-I kernel. In order to compare transconductors in a fair way, a normalized signal-to-noise ratio (NSNR) is defined. The basic V-I kernels and the five classes of composite V-I kernels are then compared, leading to insight in the key mechanisms that affect NSNR. Symbolic equations are derived to estimate NSNR, while simulations with more advanced MOSFET models verify the results. The results show a strong tradeoff between NSNR and transconductance tuning range. Resistively generated MOSFETs render the best NSNR results and are robust for future technology developments.

Systematic comparison of HF CMOS transconductors

The effectiveness of I/sub DDQ/ testing in deep sub-micron is threatened by the increased transistor sub-threshold leakage current. In this article, we survey possible solutions and propose a deep sub-micron I/sub DDQ/ test mode. The methodology provides means for unambiguous measurements of I/sub DDQ/ components and defect diagnosis. The effectiveness of the test mode is demonstrated with a real life example.

Deep sub-micron I/sub DDQ/ testing: issues and solutions

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Deep Sub-Micron IDDQ Testing: Issues and Solutions

Analog applications of MOS transistors in integrated circuits impose enhanced requirements on the compact MOS models used in circuit simulators. Here we present for the Philips MOS MODEL 9 the successful confrontation with these analog requirements, the scaling of parameters with geometry, the accuracy of the model over the whole geometry range of a process, its capabilities in the description of various processes at least down to 0.35 /spl mu/m and a comparison with advanced analog models available in commercial circuit simulators.<<ETX>>

Compact MOS modelling for analog circuit simulation

Analog applications of MOS transistors in integrated circuits impose enhanced requirements on the compact MOS models used in circuit simulators. Here we present for the Philips MOS MODEL 9 the successful confrontation with these analog requirements, the scaling of parameters with geometry, the accuracy of the model over the whole geometry range of a process, its capabilities in the description of various processes at least down to 0.35 /spl mu/m and a comparison with advanced analog models available in commercial circuit simulators. >

R.M.D.A. Velghe

Papers

Compact MOS modelling for analog circuit simulation

Compact MOS modeling for analog circuit simulation