In the High Efficiency Video Coding (HEVC) standard, a notation of the transform unit (TU) is introduced with four different sizes, i.e., 4 $\times$ 4, 8 $\times$ 8, 16 $\times$ 16, and 32 $\times$ 32, which results in at least two problems in the use of discrete cosine transform/inversed discrete cosine transform (DCT/IDCT). One is changeable input/output format presented by DCT/IDCT when it deals with TUs of different sizes, which intensifies the nonconformity during the data exchange with other modules. The other is the demand for high throughput to traverse the vast possible TU partitions to find the best one, which would be easily dragged by an inefficient data exchange method. To solve this problem, a parallel-access data mapping method based on single-port static random access memory devices (SRAMs) is proposed in this brief. It can be applied to the data exchange buffers around DCT/IDCT in HEVC encoders to fulfill a high-throughput data exchange. Here, parallel access means one row of 1 $\times$ 32 pixels, two rows of 1 $\times$ 16 pixels, four rows of 1 $\times$ 8 pixels, or four rows of 1 $\times$ 4 pixels could be accessed in one cycle depending on the specific size of the current TU.

A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs

A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding

In the High Efficiency Video Coding (HEVC) standard, the Largest Coding Unit (LCU) is already expanded to 64×64 blocks, which makes the memory cost much higher when compared with H.264 standard. To be more specific, the storage space needed for the coefficients in one LCU is as large as 8 KB. Worse still, a new notation of Transform Unit (TU) is introduced in HEVC to better improve the coding performance, which has 4 different candidate sizes and needs to be traversed to find the best TU partition. Thus, a large number of extra memory would be needed to store the temporary data during the searching process, which makes the total memory cost unbearable. In order to solve such a problem, this paper proposed a two-stage storage strategy for these memory, which fully utilized the feature of transform coefficients. When compared with normal methods, this design shows an obvious advantage both in the area cost and in the power assumption.

A SRAM-saving two-stage storage strategy for the coefficients memories in HEVC encoders

Video coding is used for lot of multimedia purposes like video conferencing, digital storage media, Internet streaming and television broadcasting. This paper presents a new design for the implementation of Full-Search (FS) Variable Block Size (VBS) Motion Estimation (ME), which is a key issue of different video compression standards such as MPEG-1, MPEG-2, MPEG-4 Visual, H.261, H.263 and H.264. The FS algorithm is widely used for implementation of ME in video compression algorithms. This design is fully parametric in terms of block size, which is variable, and the Sum of Absolute Differences (SAD) is presented by re-using the outputs. The design features high efficiency in terms of operating frequency and reduction in hardware complexity. These architectures are designed using Verilog Hardware Description Language (HDL) and the functionalities are verified using ModelSim Simulator. For two different designs, namely 1-D and 2-D systolic architectures are analyzed in terms of frequency, gate count, total power. The design is synthesized using CADENCE RTL compiler with TSMC 90nm standard cell library. The operating frequency of 1-D design is 323.20 MHz and 2-D design is 166.67 MHz and the gate count for 1-D is around 5k and for 2-D is around 21k gates and these designs can treat up to 41 Motion Vectors.

2-Dimensional systolic architecture for H.264/AVC variable block size motion estimation

This paper provides an advancement in earlier low and high efficient entropy encoder architecture for H.264/AVC which contains all three entropy encoding methods available in the H.264/AVC standard, by replacing simple CAVLC encoder used by high-throughput CAVLC encoder and CABAC encoder by real-time multi-bin CABAC encoder in order to further increase overall throughput of the system. The highthroughput CAVLC encoder that uses a dual-coefficient scanning phase which determines all the required data for encoding phase which helps in improving the speed of the encoding phase. And real-time multi-bin CABAC encoder implements the parallelism among the steps of CABAC encoding operation and thus achieves the increased throughput. The proposed architecture is expected to achieve higher throughput as compared to the present architecture but at the cost of increased complexity.

/pdf/high-throughput-entropy-encoder-architecture-for-h-264-avc-1vnpq74msq.pdf

High-Throughput Entropy Encoder Architecture for H. 264/AVC

The demand for better quality pictures, smaller sizes, lower energy consumption, lower cost of appliances has been a fuel for creation of better compression standards and great compression rate. The outstanding compression competence of H.264/AVC is extensively used for video conferencing, online streaming and for HD television. Context Adaptive Binary Arithmetic Coding (CABAC) encoder is a vital part in H.264/AVC (Advanced Video Coding) main and high profiles that provides a real time encoding video of ultra high resolution. CABAC compresses the components in the video signal according to the probability of those elements in a given context. CABAC encoder provides great compression rate over Context-Adaptive Variable Length Coding (CAVLC) baseline entropy encoder. An entropy encoder is a scheme used for lossless compression. A video sequence is a combination of bits which is referred as syntax element. The allocation of bits in various Syntax Elements (SE) [3] is analysed for the reduction in large amount of bit level operations involved and computational complexity involved. An optimised scheme for accessing the contexts and a Binary Arithmetic Encoder (BAE) capable of processing four bits simultaneously is presented. Hence parallelism and throughput is achieved by the means of reduction in syntax and bit level dependency. The proposed fully hardwired encoder is synthesised towards a 90nm CMOS cell library in ASIC flow using Cadence RTL Compiler.

A high speed real time multi-bin CABAC encoder for ultra high resolution video

The demand for better quality pictures, smaller sizes, lower energy consumption, lower cost of appliances has been a fuel for creation of better compression standards and great compression rate. The outstanding compression competence of H.264/AVC is extensively used for video conferencing, online streaming and for HD television. Context Adaptive Binary Arithmetic Coding (CABAC) encoder is a vital part in H.264/AVC (Advanced Video Coding) main and high profiles that provides a real time encoding video of ultra high resolution. A CABAC compresses the components in the video signal according to the probability of those elements in a given context. CABAC encoder provides great compression rate over Context-Adaptive Variable Length Coding (CAVLC) baseline entropy encoder. An entropy encoder is a scheme used for lossless compression. A video sequence is a combination of bits which is referred as syntax element. The allocation of bits in various Syntax Elements (SE) [3] is analysed for the reduction in large amount of bit level operations involved and computational complexity involved. An optimised scheme for accessing the contexts and a Binary Arithmetic Encoder (BAE) capable of processing four bins per cycle m nm, is presented. Hence parallelism and throughput is achieved by the means of reduction in syntax and bit level dependency. The proposed fully hardwired encoder is synthesised towards a 90nm CMOS cell library in ASIC flow using Cadence RTL Compiler.

A real time multi-bin CABAC encoder for ultra high resolution video

By the arrival of latest video standards viz. MPEG-4 part 10 and H.264/H.26L, the usages of Advanced Video Coding (AVC) especially in the part of Variable Block Size (VBS) Motion Estimation (ME) are rising. A new architecture is developed for variable block size motion estimation using full search algorithm in this paper. There are two calculations carried out in this paper block size, which is variable, and another is the Sum of Absolute Differences (SAD), which are presented by recycling the outputs of reduced sub-block calculations. Mechanism that is incorporated by every processing element is shuffling mechanism. HDL verification is done through ModelSim simulator to verify the functionality. The design is implemented using TSMC 90nm CMOS technology. The frequency of the motion estimation block is 323.20 MHz, which can treat up to 41 Motion Vectors (MV).

https://ieeexplore.ieee.org/iel7/6522357/6528464/06528478.pdf

R. M. Niyas

Papers

A high speed real time multi-bin CABAC encoder for ultra high resolution video

A real time multi-bin CABAC encoder for ultra high resolution video

High speed architecture for Variable Block Size Motion Estimation in H.264