Current very-large-scale-integration (VLSI) technology allows the manufacture of large-area integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in yield-reducing manufacturing defects, whose severity grows proportionally with the size and density of the chip. Consequently, the development and use of yield-enhancement techniques at the design stage, to complement existing efforts at the manufacturing stage, is economically justifiable. Design-stage yield-enhancement techniques are aimed at making the integrated circuit "defect tolerant", i.e., less sensitive to manufacturing defects. They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of defect-tolerant chips must rely on accurate yield projections. This paper reviews the currently used statistical yield-prediction models and their application to defect-tolerant designs. We then provide a detailed survey of various yield-enhancement techniques and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits.

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Defect tolerance in VLSI circuits: techniques and yield analysis

Three hypotheses are formulated. First, in the "design space" of possible electronic circuits, conventional design methods work within constrained regions, never considering most of the whole. Second, evolutionary algorithms can explore some of the regions beyond the scope of contentional methods, raising the possibility that better designs can be found. Third, evolutionary algorithms can in practice produce designs that are beyond the scope of conventional methods, and that are in some sense better. A reconfigurable hardware controller for a robot is evolved, using a conventional architecture with and without orthodox design constraints. In the unconstrained case, evolution exploited the enhanced capabilities of the hardware. A tone discriminator circuit is evolved on an FPGA without constraints, resulting in a structure and dynamics that are foreign to conventional design and analysis. The first two hypotheses are true. Evolution can explore the forms and processes that are natural to the electronic medium, and nonbehavioral requirements can be integrated into this design process, such as fault tolerance. A strategy to evolve circuit robustness tailored to the task, the circuit, and the medium, is presented. Hardware and software tools enabling research progress are discussed. The third hypothesis is a good working one: practically useful but radically unconventional evolved circuits are in sight.

Explorations in design space: unconventional electronics design through artificial evolution

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Towards Robust Integrated Circuits: The Embryonics Approach

The growth and operation of all living beings are directed by the interpretation, in each of their cells, of a chemical program, the DNA string or genome. This process is the source of inspiration for the Embryonics (embryonic electronics) project, whose final objective is the design of highly robust integrated circuits, endowed with properties usually associated with the living world: self-repair (cicatrization) and self-replication. The Embryonics architecture is based on four hierarchical levels of organization. (1) The basic primitive of our system is the molecule, a multiplexer-based element of a novel programmable circuit. (2) A finite set of molecules makes up a cell, essentially a small processor with an associated memory. (3) A finite set of cells makes up an organism, an application-specific multiprocessor system. (4) The organism can itself replicate, giving rise to a population of identical organisms. We begin by describing in detail the implementation of an artificial cell characterized by a fixed architecture, showing that multicellular arrays can realize a variety of different organisms, all capable of self-replication and self-repair. In order to allow for a wide range of applications, we then introduce a flexible architecture, realized using a new type of fine-grained field-programmable gate array whose basic element, our molecule, is essentially a programmable multiplexer. We describe the implementation of such a molecule, with built-in self-test, and illustrate its use in realizing two applications: a modulo-4 reversible counter (a unicellular organism) and a timer ( a complex multicellular organism). We describe our ongoing research efforts to meet three challenges: a scientific challenge, that of implementing the original specifications formulated by John von Neumann for the conception of a self-replicating automaton; a technical challenge, that of realizing very robust integrated circuits capable of self-repair and self-replication; and a biological challenge, that of attempting to show that the microscopic architectures of artificial and natural organisms, i.e., their genomes, share common properties.

Toward robust integrated circuits: The embryonics approach

Experiences in Fault Tolerant Computing, 1947-1971.- Evolution of Fault Tolerant Switching Systems in AT&T.- Fault Tolerance in Tandem Computer Systems.- Evolution of Reliable Computing in Hitachi and Autonomous Decentralized System.- A History of Research in Fault Tolerant Computing at SRI International.- The Evolution of Fault Tolerant Computing at the Charles Stark Draper Laboratory, 1955-85.- The Evolution of Fault Tolerant Computing at the Jet Propulsion Laboratory and at UCLA: 1955-1986.- Dependable Computing and Fault Tolerance at LAAS: a Summary.- Reliable Digital Systems and Related Stanford University Research.- Design Fault Tolerance.- The Evolution of Fault Tolerant Computing at the University of Illinois.- The Evolution of Fault Tolerant Computing at the University of Michigan.- Experimental Research in Reliable Computing at Carnegie Mellon University.- A History of Research in Fault Tolerant Computing at the Grenoble University.- Research Activities on FTC in Japan.- The Evolution of Dependable Computing in Italy.- Fault Tolerant Computing Systems in Germany.- The Technical Committee on Fault Tolerant Computing of The IEEE Computer Society.- Biographies.- Author Index.

The evolution of fault-tolerant computing

Fault tolerance is one of the principle mechanisms for achieving high reliability, high availability in digital systems It is the survival attribute of digital systems This book brings together and discusses the most significant results scattered across the vast field of research in fault tolerance It focuses in particular on reconfiguration techniques and presents the authors' own results in the reconfiguration of processing arrays By means of dedicated arrays, they note, it is possible to build systems that are orders of magnitude more powerful than programmed computers Their treatment of networks and arrays is extensive and has wide applicabilityContents: Introduction Typical Processing Arrays Failure Mechanisms and Fault Models Basic Problems of Fault-Tolerance Through Array Configuration Technologies Supporting Reconfiguration Testing Reconfiguration: An Introduction The Diogenes Approach Reconfiguration for Linear Arrays Graph-Theoretical Approaches to Reconfiguration Local Reconfiguration Global Reconfiguration Techniques: Row/Column Elimination Global Mapping: Index Mapping Reconfiguration Techniques Reconfiguration Based on Request-Acknowledge Local Protocols Reconfiguration of Multiple-Pipeline Structures Some Extensions Toward Time Redundancy Appendix: Reliability Prediction of ArraysR Negrini, M G Sami, and R Stefanelli are researchers at the Politecnico di Milano "Fault Tolerance Through Reconfiguration in VLSI and "I Arrays" is included in the Computer Systems series, edited by Herb Schwetman

Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays

The detection of and recovery from transient faults that cause errors in microprogrammed control units are addressed. Error detection is based upon a particular form of signature analysis, namely the run-time computation of a value (the signature) that depends strictly on the microprogram path (the sequence) under execution. The microprogram is statistically segmented (sequences are defined in a fixed way, at design time), and an anticipated signature is associated with each sequence. At run time, at the start of each sequence the computation of the signature is restarted, whereas at the end the computed signature is compared with the anticipated signature of the sequence. If the check is passed, the status of the control unit is saved in suitable registers, and the previously saved status is discarded. If the check fails, the last-saved status is restored (rolled back) and microprogram execution restarts from this last-saved point. >

Tolerance to transient faults in microprogrammed control units

The paper presents a policy for system-level diagnosis and error confinement in distributed systems. The class of architectures to which the policy applies is defined, and the physical supports needed are described. It is proved that mechanisms presented permit reaching deterministic results of diagnosis in finite time (thus avoiding deadlock or starvation effects) and that system-level error confinement is effectively obtained. Mechanisms are implemented by means of software.

Policies for System-level Diagnosis in a Non-Hierarchic Distributed System

Image Processing often involves convolutions and Fourier Transforms (DFT and FFT): these specific operations are well implemented by means of a systolic multi-pipeline structure.

Fault tolerance in imaging-oriented systolic arrays

This paper treats (Multiple) Interconnection Networks (MINs), dealing in particular with their adoption in supercomputing architectures. The main properties and characteristics of MINs are recalled and some typical parallel computer architectures adopting MINs are summarized. Two main application classes of MINs are considered: parallel computer systems implemented by connecting together powerful processors and large shared memories, and dedicated supercomputing structures directly implementing highly parallel algorithms. For both application classes, the adoption of fault tolerance methods is discussed. Fault tolerance can be usefully adopted both to overcome production defects and faults arising during systems working life. Classic approaches to fault tolerance in MINs for parallel computer systems and some recent results in the less known field of fault tolerance in dedicated supercomputing structures are surveyed.

R. Negrini

Papers

Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays

Tolerance to transient faults in microprogrammed control units

Policies for System-level Diagnosis in a Non-Hierarchic Distributed System

Fault tolerance in imaging-oriented systolic arrays

Interconnection Networks for Highly Parallel Supercomputing Architectures