A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates load/store requests to transfer data between the system memory and the microprocessor. The microprocessor also includes a stream prefetch unit that generates a plurality of prefetch requests to prefetch the data stream from the system memory into the microprocessor. The prefetch requests specify the stream prefetch priority. The microprocessor also includes a bus interface unit (BIU) that generates transaction requests on the bus to transfer data between the system memory and the microprocessor in response to the load/store requests and the prefetch requests. The BIU prioritizes the bus transaction requests for the prefetch requests relative to the bus transaction requests for the load/store requests based on the stream prefetch priority.

Microprocessor with improved data stream prefetching

This survey exposes the problems related to virtual caches in the context of uniprocessor (Part 1) and multiprocessor (Part 2) systems. We review proposed solutions that have been implemented or proposed in different contexts. The idea is to catalog all solutions, past and present, and to identify technology trends and attractive future approaches. We first overview the relevant properties of virtual memory and of physical caches. To solve the virtual-to-physical address bottle-neck, processors may access caches directly with virtual addresses. This survey introduces the problems and discusses solutions in the context of single-processor systems.

Virtual-address caches. Part 1: problems and solutions in uniprocessors

Most modern cores perform a highly-associative transaction look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it with L1 cache access, but this overlap does not hide the power dissi-pated by TLB lookups. It can even exacerbate the power dissipation by requiring higher associativity L1 cache. With today's concern for power dissipation, designs could instead adopt a virtual L1 cache, wherein TLB access power is dissipated only after L1 cache misses. Unfortunately, virtual caches have compatibility issues, such as supporting writeable synonyms and x86's physical page table walker. This work proposes an Opportunistic Virtual Cache (OVC) that exposes virtual caching as a dynamic optimization by allowing some memory blocks to be cached with virtual addresses and others with physical addresses. OVC relies on small OS changes to signal which pages can use virtual caching (e.g., no writeable synonyms), but defaults to physical caching for compatibility. We show OVC's promise with analysis that finds virtual cache problems exist, but are dynamically rare. We change 240 lines in Linux 2.6.28 to enable OVC. On experiments with Parsec and commercial workloads, the resulting system saves 94-99% of TLB lookup energy and nearly 23% of L1 cache dynamic lookup energy.

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Reducing memory reference energy with opportunistic virtual caching

A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor (200-216). Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined (214-216) for the memory location identified by the memory micro-instruction. Once the memory-type is known the memory micro-instruction is processed (218-230) in accordance with any one of a number or processing protocols including write-through processing (220), write-back processing (222), write-protect processing (224), restricted-cacheability processing (226), uncacheable speculatable write-combining processing (230), or uncacheable processing (228). By providing memory-type information explicitly within the microprocessor the protocol by which the micro-instruction is processed may be efficiently tailored to the memory-type. In an exemplary embodiment, the microprocessor is an out-of-order microprocessor (200) capable of generating speculative memory microinstructions (202-204).

Method and apparatus for processing memory-type information within a microprocessor

The PowerPC, a new RISC architecture derived from IBM’s POWER architecture, is currently available as an open-system standard. To provide both software compatibility among PowerPC processors and maximum implementation flexibility, its designers specified the PowerPC architecture in four books. As we show here, Book 1 describes the user-mode programming model and instruction set common to all PowerPC processors.

The PowerPC user instruction set architecture

The PowerPC is a new RISC architecture derived from IBM's POWER architecture. The changes made to POWER simplify implementations, increase clock rates, enable a higher degree of superscalar execution, extend the architecture to 64 bits, and add multiprocessor support. For compatibility with existing software, the developers retained POWER's basic instruction set, opcode assignments, and programming model. >

R. Oehler

Papers

Evolution of the PowerPC architecture