We report on a trace-driven simulation study to examine the effect of a two-level cache hierarchy in uniprocessors. A simulation model of a multiple-cycle-per-instruction processor was constructed to estimate the total cycles required to execute a synthetic benchmark. Results show that a second-level cache can be used to increase system performance when main memory access times are large relative to CPU cycle time. For example, the addition of a 4-cycle, 64K second-level cache following a 1-cycle, 8K first-level cache increases performance by 15 percent when used in a system with a 15-cycle primary memory. Second level caches are shown to be particularly effective when used behind small on-chip caches; adding an 8K second-level to a 1K first-level increases performance by 26 percent, assuming similar parameters. We also evaluate the performance impact of different write strategies and separate I and D caches.

A simulation study of two-level caches

The system consists of multiprocessors P1 to Pn connected to a central memory (9) by means of a single bus (8). Each processor comprises a central-processing unit (1) and a cache memory (2,4). The method consists in dividing the cache memory into two levels (2,4), in causing the write operations issued by the central-processing unit of each processor to be performed in the two cache-memory levels by virtue of a procedure for immediate writing in order to keep, in the second level (4), an updated copy of the information contained in the first level (2), and in updating the corresponding information in the central memory (1) from the second cache-memory level (4) by a procedure for delayed writing. Application: information-processing systems.

Cache management method in a multiprocessor system

LE SYSTEME EST CONSTITUE PAR DES MULTIPROCESSEURS P A P RELIES A UNE MEMOIRE CENTRALE 9 AU MOYEN D'UN BUS UNIQUE 8. CHAQUE PROCESSEUR COMPREND UNE UNITE CENTRALE 1 ET UNE ANTEMEMOIRE 2, 4. LE PROCEDE CONSISTE A SIMULER L'ANTEMEMOIRE EN DEUX NIVEAUX 2, 4, A FAIRE EFFECTUER LES ECRITURES EMISES PAR L'UNITE CENTRALE DE CHAQUE PROCESSEUR DANS LES DEUX NIVEAUX D'ANTEMEMOIRE GRACE A UN PROCESSUS D'ECRITURES IMMEDIATES POUR MAINTENIR UNE COPIE A JOUR DANS LE SECOND NIVEAU 4 DES INFORMATIONS CONTENUES DANS LE PREMIER NIVEAU 2 ET A EFFECTUER LA MISE A JOUR DES INFORMATIONS CORRESPONDANTES DANS LA MEMOIRE CENTRALE 1 DEPUIS LE SECOND NIVEAU D'ANTEMEMOIRE 4 PAR UN PROCESSUS D'ECRITURES DIFFEREES. APPLICATION : SYSTEMES DE TRAITEMENT DE L'INFORMATION.

Procede de gestion d'antememoires associees a des processeurs dans une architecture multiprocesseur a bus unique et systeme de traitement de donnees fonctionnant suivant ce procede

The authors describe a new shared cache scheme for multiprocessors (MPS) The scheme permits each processor to execute directly out of shared cache The access time is longer than that to private cache Store-through local caches are used

R.P. Fletcher

Papers

Mp-shared cache with store-through local caches