A proxy server containing a cache for retrieving information from a server and transmitting this information to multiple concurrent clients. A thread is created for each client requesting the information from the server. As long as information is contained in the cache, all the threads assume the role of a consumer thread by retrieving this information from the cache and placing it in an output stream to be sent to the client associated with each consumer thread. When one of the threads reaches the end of the information contained in the cache, it assumes the role of a producer to send a request to the server to retrieve additional information. When the producer thread receives the information from the server, it places it in an input stream for the cache. The producer thread then reverts back to a consumer thread to retrieve this information for its associated client. All other consumer threads may also retrieve this data from the cache. In retrieving information from the server, there may be multiple producers and consumers, however it is preferable that only one thread will be a producer at any given time.

Bounding delays and reducing threading overheads in caching

Several commercial and research projects have produced a variety of 'computing surfaces' based on FPGAs with some interconnection pattern. However, because the majority of these projects have constrained themselves to two-dimensional structures that can be fabricated on a single planar substrate, the interconnect patterns are fixed and severely constrain the ability of a problem to be mapped on to the prototyping system. This paper describes a simple development of the Achilles interprocessor switch. Achilles' 3D stack of processors provides a flexible and scalable system-any number of stacks may be connected together in a small volume and a user may set up a connection pattern quite different from any envisaged by the hardware designer. Simulation of control systems where there are large numbers of objects such as traffic flows, network message traffic, etc, is CPU intensive and generally requires inordinately long runs on conventional sequential processors. So we have chosen Petri Net simulation for a feasibility study for Achilles as a reconfigurable processor. This showed that the architecture is particularly suitable for Petri Net simulations as hundreds of places in a net can be simultaneously active-reducing by orders of magnitude the time necessary for simulations.

A scalable re-configurable processor

Simulation of systems for the control of large numbers of objects such as traffic flows, network message traffic, etc. is CPU intensive and may require inordinately long runs on conventional sequential processors. The article describes the Achilles reconfigurable processor and techniques for programming it to carry out Petri net simulations. Achilles is an innovative 3-dimensional stack of FPGAs. The 3D arrangement allows: (a) a large number of FPGAs to fit in a small volume, (b) a large degree of flexibility in the way individual devices are interconnected, (c) interconnection with one or more hosts with host-Achilles bandwidth being scaled up to meet requirements and (d) individual stacks to be connected together in a wide variety of patterns so that the computing power of the stack may be scaled as necessary. Bandwidths between the stack and a PC host have been measured at over 30 Mbytes/second in the first prototype of the stack: the interconnection is capable of transferring data at PCI bus speeds with the newer, faster FPGAs used in the second prototype currently under construction. This architecture is particularly suitable for Petri net simulations as hundreds of places in a net can be simultaneously active-reducing by order's of magnitude the time necessary for simulations.

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A re-configurable processor for Petri net simulation

We measured the relative performance of two support systems for parallel programming on networks of workstations: Cilk - an extension of C with dataflow semantics - and MPI - a commonly used library for message passing. Although the two systems present significantly different parallel processing models, we attempted to code the benchmark problems in similar ways. The problems selected were matrix multiplication, travelling salesman problem, quick sort, Gaussian elimination, fast Fourier transform and finite differencing. We compared run times, speed-ups and coding efficiency as measured by lines of code in our implementations of the problems. Cilk showed a speed advantage when smaller numbers of large messages are transferred in a computation, enabling it to gain more from the underlying active messages implementation. Cilk code for algorithms with natural dataflow solutions was more compact, whereas algorithms which have simple iterative 'update-in-place' styles (Gaussian elimination and finite differencing) were more efficiently expressed when MPI was used

Cilk vs MPI: comparing two very different parallel programming styles

The Achilles Router provides low latency, high bandwidth connections between processors, enabling a network of low-cost processors to perform as a high-performance parallel processor. It is also economical, being constructed from low cost Field Programmable Gate Arrays (FPGAs). These programmable devices allow it to be re-programmed for use in a variety of network topologies; they also permit ‘tuning’ the router for optimum performance in different applications. A key factor in its simplicity and performance is the 3-D structure: this allows us to build a full cross-bar switch with a wide, high-bandwidth datapath. The simple cross-bar circuit also has very low latency: we measured latencies of ~ 800ns in the hardware and 2.5μs when software overheads were included. We measured the basic performance of an inter-processor link using Achilles, and then, using a range of benchmarks with different characteristics, showed that Achilles clearly outperforms Fast Ethernet.

Performance of the Achilles Router

Achilles: high bandwidth, low latency, low overhead communication

Shared memory machines have two major overheads: keeping caches coherent and managing the multiple threads of computation which enable tolerance of very long memory latencies. Thetis is a hybrid architecture providing both shared memory and efficient message passing; it will be built from 'commodity' components and consists of sites with a small number of computation processors and a separate, programmable, auxiliary processor. The auxiliary processor performs overhead tasks, e.g. maintenance of cache directories, management of memory and thread queues; placed on its own bus, it does not block or delay memory accesses from computation processors which are not waiting for it. We describe how the use of a threaded variant of C (which has a functional style) enables the run-time system to dynamically determine coherence needs-dramatically reducing the overhead of maintaining coherent caches in a shared memory machine.

R.R. Gregg

Papers

Achilles: high bandwidth, low latency, low overhead communication

Reducing overheads in distributed shared memory systems