This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.

Embedded deterministic test

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.

Embedded deterministic test for low cost manufacturing test

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

At-speed testing of gigahertz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost high-quality self-test methodologies that can be used by processors to test themselves at-speed. Currently, built-in self-test (BIST) is the primary self-test methodology available. While memory BIST is commonly used for testing embedded memory cores, complex logic designs such as microprocessors are rarely tested with logic BIST. In this paper, we first analyze the issues associated with current hardware-based logic-BIST methodologies by applying a commercial logic-BIST tool to two processor cores. We then propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of self-test signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets and the test application program applies the tests to the components under test at the speed of the processor. Application of the novel software-based self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.

Software-based self-testing methodology for processor cores

Scan based at-speed transition fault testing of Motorola's microprocessors based on the PowerPC/spl trade/ instruction set architecture requires broad-side transition fault test patterns that have a specific launch and capture clocking sequence. We describe the concepts we developed and incorporated in the ATPG tool to support efficient generation of such test patterns to achieve high transition fault test coverage and for analysis of undetected transition faults. Using the enhanced ATPG tool, we generated 15,000 transition fault test patterns and achieved 76% test coverage for the MPC7400 microprocessor based on the PowerPC/spl trade/ instruction set architecture that has 10.5 million transistors and runs at 540 MHz.

Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC/spl trade/ instruction set architecture

This paper presents a practical case-study of using DFT techniques for speed-grading the Motorola MPC7455, a 1 GHz+ microprocessor. The effectiveness of transition fault detection, path-delay AC-scan patterns and array BIST is compared with that of functional patterns for speed-grading the parts. We discuss the capabilities and challenges of using the DFT methods based on production data.

Use of DFT techniques in speed grading a 1 GHz+ microprocessor

Functional (i.e., logic) verification of the current generation of complex, super-scalar microprocessors such as the PowerPC 604 microprocessor presents significant challenges to a project's verification participants. Simple architectural level tests are insufficient to gain confidence in the quality of the design. Detailed planning must be combined with a broad collection of methods and tools to ensure that design defects are detected as early as possible in a project's life-cycle. This paper discusses the methodology applied to the functional verification of the PowerPC 604 microprocessor.

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Functional verification methodology for the PowerPC 604 microprocessor

This paper introduces the extended /spl Delta//spl phi/ method for measuring cycle-to-cycle period jitter in PLL outputs. The theoretical basis for this method is derived from the limited condition for the average period and analytic signal theory. Sinusoidal jitter measurements verify the relationship between cycle-to-cycle period jitter and timing jitter. To validate the method, experimental data from jitter measurements on a PowerPC/sup TM/ microprocessor is analyzed in the frequency domain. Comparisons of phase quantization errors are made between the extended /spl Delta//spl phi/ method and the conventional zero-crossing method.

A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals

A method of testing a multi-core processor that includes the steps of receiving a plurality of input signals from a plurality of processor cores (100), and producing an output signal corresponding to a disable state when at least two of the plurality of input signals represent a different logic value (106). A testing device (12) includes a multiplexer (40) responsive to a plurality of input signals (24, 26, 28, 30) from a plurality of processor cores (14, 16, 18, 20), and an output driver (48) responsive to the multiplexer (40). The output driver (48) produces an output signal (62) corresponding to a disable state when at least two of the plurality of input signals (24, 26, 28, 30) represent a different logic value.

R. Raina

Papers

Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC/spl trade/ instruction set architecture

Use of DFT techniques in speed grading a 1 GHz+ microprocessor

Functional verification methodology for the PowerPC 604 microprocessor

A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals

Method of testing multi-core processors and multi-core processor testing device