Scalable multicast control-plane for optical packet forwarding engines: A multiway SVRF approach

High-performance multicast-enabled packet forwarding engines (PFEs), as an essential component of high-end switches, use a polynomial-time membership query algorithm to determine which port(s) the data packet should be forwarded. The currently widely used query algorithm is Bloom Filter (BF), which has been proven to have many fatal flaws. Another error-free membership query algorithm includes Scalar-pair Vectors Routing Forwarding (SVRF), Fractional- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N Scalar-pair Vectors Routing Forwarding (Frac- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N SVRF), and the Per-Port Prime Filter Array (P 3 FA) also have some shortcomings in space and time efficiencies. In this paper, we proposed a hybrid strategy: Divaricate Heterogeneous SVRF (DH-SVRF) scheme, which based on the P 3 FA and Frac- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N SVRF, which randomly divides all member ships into <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N groups, and each group has the same structure and is independent of each other to obtain higher time efficiency and space utilization. Finally, we also discussed the selection of the optimal egress-diversity threshold. Through mathematical modeling and simulation, we validate that the proposed DH-SVRF scheme is superior to the SVRF/Frac <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-N SVRF and traditional BF in terms of scalability, space utilization, and time efficiency in specific conditions such as appropriate egress-diversity thresholds.

DH-SVRF: A Reconfigurable Unicast/Multicast Forwarding for High-Performance Packet Forwarding Engines

In this paper, an algorithm for 32-bit integer division is proposed. The algorithm calculates the integer division of positive and negative dividends and divisors represented in sign and magnitude. It calculates the magnitudes and signs of the quotient and remainder separately based on the magnitudes and signs of the divided and divisor. In the algorithm, the magnitude of the remainder is initially set to be the dividend and is iteratively reduced until it becomes smaller than the magnitude of the divisor; afterwards the algorithm converges. A priority encoder is used to improve the convergence rate by skipping the zeros between the high bits while shifting the divisor in each iteration to be aligned with the partial remainder. The magnitude of the quotient is initially set to zero and updated based on the amount of shift in each iteration. A hardware architecture is proposed to implement the algorithm. The hardware is synthesized on an FPGA device, and its functionality was verified by ModelSim simulations. The results show that the hardware achieves a maximum operating frequency of 90.9MHz, and achieves an improvement of 31.43%, 59.12%, and 18.1%, in terms of delay, LUTs, and slices, respectively, over the most recent existing approach. MATLAB simulations were also conducted to measure the convergence rate. The MATLAB simulation results show that on average the convergences rate is less than or equal to the half of the difference between the number of bits in the dividend and the number of bits in the divisor.

A 32-bit Integer Division Algorithm Based on Priority Encoder

High-performance multicast packet switching technologies are evolving to meet the growing demand for scalability on the Internet and datacenters, etc. Implementing a high-performance switch/router relies on a polynomial-time group membership query algorithm within the Packet Forwarding Engines (PFEs) to determine whether a packet is forwarded through an egress. Among these, Bloom filter (BF)-based and Residue Number System (RNS)-based are being considered as two representatives of the membership query algorithms. However, both approaches suffer from some fatal weaknesses such as false-positive probability and time inefficiencies, especially for a carrier-grade PFE with high port-density features. According to similar properties of the RNS, we propose a simplified forwarding algorithm in this paper, named Per-Port Prime Filter Array (P3FA). The simulation results indicate that the P3FA can significantly improve space efficiencies under specific lower egress-diversities conditions. Under the same space constraints, P3FA improves multicast and unicast time efficiency by 1 to 4 orders of magnitude in the port-density 16–1024 range compared to previous works. Although it comes at the expense of hardware cost, it is still acceptable compared to recently improved previous work.

P3FA: Unified Unicast/Multicast Forwarding Algorithm for High-Performance Router/Switch

In the past years, the demand for high-precision arithmetic has significantly increased, which raised the need for devices that can handle high-precision computations. Therefore, in this paper, we propose a hardware for high-precision division. The proposed hardware is implemented for 1024 bits, and it can be easily extended to larger bits. The hardware performs division on integer numbers represented in sign and magnitude, and produces quotient and remainder. A priority encoder is used to improve the convergence rate, and to make the dividend and divisor lengths not required as inputs. To reduce complexity, most of the components were implemented in two levels. We provide an upper limit and a closed-form expression for the convergence rate. We synthesized the hardware on a Field-Programmable Gate Array (FPGA) device. We simulated the hardware at the bit level in Matlab using Monte Carlo simulations. We also simulated the hardware in ModelSim. Compared to the existing approaches, the results show that for 64-bit division, our hardware reduces the number of LUTs and slices by 18.4% and 67.5%, respectively, and improves delay by 50.3%. As for 256-bit division, our hardware reduces the number of slices by 60.7% and improves delay by 33.25%, however, it increases the number of LUTs by 11.32%.

High-Precision Priority Encoder Based Integer Division Algorithm

Division is the highest latency arithmetic operation in present digital architectures and high-performance computing systems; as such drives the demand for efficient hardware division units. Accordingly, this paper proposes a novel architecture for a nonrestoring divisor based on the radix-2 signed-digit (SD2) representation. This notation has been chosen to achieve fast computation, as proposed by Avizienis (IEEE Transactions on Electronic Computers, vol. EC-10, no. 3, pp. 389-400, Sep. 1961), but the architecture presented in this paper, due to its structure and the definition of the cell implementing its architecture, saves area as well. The proposed divisor architecture is able to achieve a delay of order , similar to the solution presented by Takagi (IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, E89-A, no. 10, pp. 2874-2881, 2006) being considered as the state of the art, instead of other solutions that give growth. This is in line with the fact that even if our carry-chains have a less impact on the circuit the basic cell is larger compared to the one proposed by Takagi Our cells are larger that those proposed in literature, considering them as single circuit, but considering the overall structure there is a saving of some 40% in the number of gates and a gain of 55% in terms of power saving when compared with the state of the art.

R Stefanelli

Papers

A New Compact SD2 Positive Integer Triangular Array Division Circuit