We present ultra-low-voltage circuit design techniques for a fractional-N RF synthesizer with two-point modulation which was realized in 90-nm CMOS using only regular VT devices.; the voltage controlled oscillator, phase-frequency detector and charge pump operate from a 0.5 V supply while the divider uses a 0.65 V supply. The frequency synthesizer achieves a phase noise better than -120 dBc/Hz at 3 MHz, while consuming 6 mW. A calibration technique to equalize the gain between the two modulation ports is introduced and enables phase/frequency modulation beyond the loop bandwidth of the phase-locked loop. Measurement results for 2-Mb/s GFSK modulation are presented.

A 0.65-V 2.5-GHz Fractional-N Synthesizer With Two-Point 2-Mb/s GFSK Data Modulation

A digital intensive PLL featuring a digital filter in parallel with an analog feed-forward path and a digital controlled oscillator (DCO) is presented. Digital loop filter replaces analog passive filter to reduce chip area and associated gate-leakage in advanced process. It also allows the PLL loop gain and DCO gain to be digitally calibrated to within 100 ppm within 50 mus. Such fine frequency resolution enables the PLL to accurately compensate for the loop parameter variation due to process, voltage and temperature (PVT). The analog feed-forward path is insensitive to quantization error of fractional-N divider and DCO nonlinearity. Direct modulating the DCO frequency and phase through the analog feed-forward path, and compensating the modulating signal digitally for the DCO gain variation are demonstrated. At 3.6 GHz all fractional spurs are under - 75 dBc. The phase noise at 400 kHz and 3 MHz are -115.6 dBc/Hz and -134.9 dBc/Hz, respectively. The chip is fabricated in a 0.13 mu m CMOS process, and occupies an active area of 0.85 mm2 and draws 40 mA from a 1.5 V supply including all auxiliary circuitry.

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes

We present an analog subsampling PLL based on a digital-to-time converter (DTC), which operates with almost no performance gap (176/198 fs RMS jitter) between the integer and the worst case fractional operation, achieving −246.6 dB FOM in the worst case fractional mode. The PLL is capable of two-point, 10 Mbit/s GMSK modulation with −40.5 dB EVM around a 10.24 GHz fractional carrier. The analog nonidealities—DTC gain, DTC nonlinearity, modulating VCO bank gain, and nonlinearity—are calibrated in the background while the system operates normally. This results in ~15 dB fractional spur improvement (from −41 dBc to −56.5 dBc) during synthesis and ~15 dB EVM improvement (from −25 dB to −40.5 dB) during modulation. The paper provides an overview of the mechanisms that contribute to performance degradation in DTC-based PLL/phase modulators and presents ways to mitigate them. We demonstrate state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

A new frequency synthesizer with low-power and short settling time is introduced. With two-point channel controls for an integer-N PLL, we have achieved a near zero settling time for any frequency change in 2.4GHz ZigBee band. By utilizing a vertical-NPN parasitic transistor for the VCO biasing, the close-in phase noise has been improved by 5dB from the case of MOS biasing. A modified-TSPC topology is proposed for low-voltage frequency divider circuits. Using the 1.2V supply voltage for 0.18mum CMOS, the power consumption is only 4.2mW and the phase noise is -116.5dBc/Hz at 1MHz offset

4.2W CMOS Frequency Synthesizer for 2.4GHz ZigBee Application with Fast Settling Time Performance

An all-digital reconfigurable multi-output clock generator is presented. A digital phase-locked loop provides a high-frequency clock to multiple independent open loop $\Delta \Sigma $ fractional dividers (FDIVs). A high resolution digital-to-time converter (DTC) whose range is calibrated in background is used to achieve low-jitter performance that is insensitive to process, voltage, and temperature variations. The proposed open loop FDIV operates over a wide frequency range of 20 MHz–1 GHz, and has programmable spread spectrum modulation and instantaneous frequency switching capabilities. Fabricated in a 65-nm process, the prototype FDIV occupies an active area of 0.017 mm2. At 1-GHz output frequency, it consumes 3.2 mW from 0.9-V supply and achieves a worst case integrated jitter of 1.44 psrms.

Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers

This paper presents a fractional-N modulator architecture that uses the technique of two-point-modulation. This technique allows direct modulation of the VCO within the closed loop of a high resolution PLL based fractional-N frequency synthesizer, without restriction due to loop bandwidth and PLL dynamics. A prototype transmitter was implemented using the GSM standard to verify the superior performance predicted by simulation. The core element of this new modulator architecture is a PLL-based fractional-N frequency synthesizer. This prototype synthesizer consists essentially of a full custom IC for the analog section, and the digital functionality was implemented in a filed programmable gate array (FPGA). The analog circuitry was fabricated in a 25 GHz BiCMOS process with 0.8 /spl mu/m as minimum feature size. Measurements of the spectrum for the GSM modulated signal and of the demodulated signal show that the strict demands of the GSM specification can be met.

R. Vuketich

Papers

GSM 900/DCS 1800 fractional-N modulator with two-point-modulation