R.E. Bryant proposed a method to handle logic expressions (IEEE Trans. Comp., vol.25, no.8, p.667-91, 1986) which is based on binary decision diagrams (BDD) with restriction; variable ordering ix fixed throughout a diagram. The method is more efficient than other methods proposed so far and depends heavily on variable ordering. A simple but powerful algorithm for variable ordering is developed. The algorithm tries to find a variable ordering which minimizes the number of crosspoints of nets when the circuit diagram is drawn. This is applied to the Boolean comparison of ISCAS benchmark circuits for test pattern generation. The results show that binary decision diagrams (BDD) with the proposed ordering method can verify almost all benchmark circuits in less than several central processor unit (CPU) minutes, which is one hundred times (or more) faster than times reported in the literature. Some techniques for circuit evaluation ordering are also mentioned. >

Evaluation and improvement of Boolean comparison method based on binary decision diagrams

This paper describes a top-down, constraint-driven design methodology for analog integrated circuits. Some of the tools that support this methodology are described. These include behavioral simulation tools, tools for physical assembly, and module generators. Finally, examples of behavioral simulation with optimization and physical assembly are provided to better illustrate the methodology and its integration with the tool set.

A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits

ILAC (interactive layout of analog CMOS circuits) is a process-independent tool that automatically generates geometrical layout for analog CMOS cells from a circuit description. ILAC handles typical analog layout constraints such as device matching, symmetry, and distance and coupling constraints. ILAC supports user-specified constraints on cell height and input/output pin locations. Together with the design tool IDAC (interactive design for analog circuits), ILAC makes a fully functional analog CMOS cell compiler that automatically produces geometrical layout from functional specifications for a library of circuits including amplifiers, voltage and current references, comparators, oscillators, and A/D (analog-to-digital) converters. >

ILAC: an automated layout tool for analog CMOS circuits

A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower-level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing, and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach.

Automation of IC layout with analog constraints

STAIC is an interactive design tool that synthesizes CMOS and BiCMOS analog integrated circuits that conform to specified performance constraints. STAIC features an input modeling language for entering hierarchical circuit descriptions and a symbolic/numeric solve unit that dynamically integrates analytical model equations across hierarchical boundaries. The output of the solver is a flattened homogeneous model that is customized to a user-specified topology and set of performance specifications. The output is thus tailored for optimization and other numerically intense design exploration procedures. All model descriptions include physical layout so that important net parasitics may be fully accounted for during design evaluation. Synthesis proceeds via a successive solution refinement methodology. Multilevel models of increasing sophistication are used by scan and optimization modules to converge to what is likely a globally optimal solution. Design experiments have shown that STAIC can produce satisfactory results. >

STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits

A description is given of ILAC (Interactive Layout of Analog CMOS Circuits), a CAD (computer-aided design) tool that automatically generates geometrical layout for analog CMOS leaf cells from netlist information and user-specified constraints on cell bounds and input/output locations. ILAC is the companion tool of IDAC, a design tool that sizes analog CMOS circuits from a library of proven schematics given a set of functional specifications and technological parameters. Unlike existing analog silicon compilers that use some predefined placement for a specific type of circuit, ILAC determines an optimal layout for any circuit and any set of input parameters. >

R. Zinszner

Papers

ILAC: an automated layout tool for analog CMOS circuits