According to Moore’s law, there have been numerous technological advancements that are currently being processed. The controllability of the device has improved significantly since a basic MOSFET with a single control gate was changed to one with many control gates. This study examines the DC metrics of a sub-5 nm node, junctionless gate, and vertically stacked nanowire field effect transistor (FET). In order to improve the factors I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> , I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> , switching ratio (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> /I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> ), DIBL, and Sub threshold Swing, the device is tuned and compared. Here, a variety of dielectric-permitivity (k) values and symmetric and asymmetric spacing are employed with spacers. 3D-VTCAD is the tool used to evaluate these characteristics. Therefore, a JL nanowire FET with the best design guarantees that it can be a candidate for low-power and superior linearity technology nodes in the future. 

Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs

The electromagnetic spectrum is one of nature’s meagre resources. The requirements of wireless communication cannot be satisfied by the new spectrum allocation plan. A policy of self-driven spectrum allocation results as a result. Cognitive radio (CR) engineering is a brilliant technique to maximise spectrum utilisation in rapidly changing environments by identifying unusable and underutilised bandwidth. One of the information strategies of intellectual radio is range detecting, which uses self-persuaded range allocation techniques to use open range to determine the existence of critical clients in the approved recurrence band. Energy location and cyclostationary highlight recognition are the two main factors that determine range detection. Energy recognition is a key method of range detection, but it becomes discouraging at low signal to noise ratios. With a cost of the highest degree of execution complexity, the critical cyclostationary highlight recognition based on cyclic range assessment may successfully identify weak signs from crucial clients. This project is aimed at implementing a useful range detecting mechanism in a field programmable door show with meticulous precision for CR. The adaptive absolute-self-coherent-restoral algorithm, specifically using the truncation multiplier, is a new spectrum sensing system. The proposed architecture, which makes use of a truncation multiplier, was created using the Xilinx approach. This study suggests an efficient spectrum sensing technique that makes use of the Adaptive Absolute Score (AAS) algorithm and SQRT-based Carry Select Adder (CSLA). The TM-CSLA design includes 228 LUT for the Spartan 6 device, which is fewer than the other architectures.

/pdf/truncation-multiplier-based-cognitive-radio-spectrum-13u89q61.pdf

Truncation Multiplier-Based Cognitive Radio Spectrum Analyzer for Nanomedical Applications

In this paper, we propose design and implementation of novel line adder architecture capable of adding multiple addends in a single step. The architecture is derived based on addition algorithm from Shuddha system of vedic mathematics. The adder architecture is particularly suitable for a class of applications, such as FIR filter, where multiple operands are required to be added. The implementation is particularly suited for portable systems where area and power consumption are highly constrained. We then quantitatively compare proposed adder architecture against popular Parallel-prefix adder architectures for different wordlengths (N = 4, 8, 16 and 32 bits). All the architectures are implemented on Genesys2 board (Xilinx part number xc7k325t-2ffg900c) using VHDL coding and Xilinx Vivado 2016.2 platform. Standard performance metrics such as FPGA device utilization (number of slices and logic LUTs), Power Consumption and Performance are considered for comparison. Results indicate that proposed vedic adder occupies 35.12 % lesser logic LUTs and 28.71 % lesser slices than any other adder architectures, under consideration, while at the same time, there is an improvement of 9.1 % in on-chip FPGA power consumption than all other adder architectures. The performance of vedic adder architecture draws parallel with that of fastest prefix adder being considered.

Implementation and Performance Evaluation of Novel Line Adder Architecture for Portable Systems : A Vedic Mathematics Approach

One of India’s fastest-growing industries is the manufacturing sector centered on exports. Additionally, it has a greater impact on the economic development of India. Technology in the export-oriented manufacturing sector makes a significant contribution to the rise in productivity, which also boosts profits. The study’s major goal is to learn more about the adoption of the 14.0 ICT system by manufacturing enterprises with reference to MSMEs and to evaluate its efficacy. In order to gather information for this goal, a survey approach was used, with the dimensions of ICT infrastructure, ICT hardware, software, and information systems, as well as people and human resource factors, as the instruments. Multiple regression and descriptive statistics were used to evaluate the data on a sample size of 7 businesses from the Pondicherry region. The conclusion is that firms have a significant gap in their ICT preparedness in terms of ICT infrastructure, ICT hardware, software, and information systems, and this must be treated seriously by the businesses if technology advancement is to continue in the future.

/pdf/ict-system-for-14-0-adoption-comparative-study-to-assess-the-2gjavhys.pdf

ICT System for 14.0 Adoption: Comparative Study to Assess the Readiness in Manufacturing MSMEs

According to Moore’s law, there have been numerous technological advancements that are currently being processed. The controllability of the device has improved significantly since a basic MOSFET with a single control gate was changed to one with many control gates. This study examines the DC metrics of a sub-5 nm node, junctionless gate, and vertically stacked nanowire field effect transistor (FET). In order to improve the factors ION, IOFF, switching ratio (ION/IOFF), DIBL, and Sub threshold Swing, the device is tuned and compared. Here, a variety of dielectric-permitivity (k) values and symmetric and asymmetric spacing are employed with spacers. 3D-VTCAD is the tool used to evaluate these characteristics. Therefore, a JL nanowire FET with the best design guarantees that it can be a candidate for low-power and superior linearity technology nodes in the future.

ABSTRACT An approximate carry select adder (CSLA) with reverse carry propagation (RCSLA) is showed in this work. This RCSLA was designed with reverse carry propagate full adder (RCPFA). In RCPFA structure, the carry signal propagates in the reverse direction that is from MSB part to LSB part, then the carry input has greater importance compared to the output carry. Three types of implementations were designed in RCPFA based on the design parameters. This method was applied to RCA & CSLA to design other types of approximate adders. These designs and simulations were done in CADENCE Software tool with 45 nm COMS technology. The design parameters of the three CSLA implementations with RCPFA are compared with the existing CSLA adders.

Design of approximate reverse carry select adder using RCPA

Low power VLSI implementation of real fast Fourier transform with DRAM-VM-CLA

In today's the rapid development of technology, area, delay and power are the most important factors to design any kind of algorithm on Field Programmable Gate Arrays (FPGA). The aim of this work is to design an efficient 32-point Radix-2 memory based Real Fast Fourier Transform (RFFT) computation for the real-valued signals. The proposed RFFT architecture can deliver a maximum throughput rate and lesser hardware complexity by using a Processing Element (PE), which is utilized in the RFFT architecture. Compared with the previous works the proposed RFFT architecture with Carry Increment Adder (CIA) and pipelined adder technique has a main advantage of less hardware usage and moreover reduction in the computation cycles. The experimental results shows that Look-up tables (LUT), slices, flip flops, frequency improved in RFFT architecture with CIA and pipelined adder compared with the existing methods.

Low-Complexity High Speed Memory Based Real Fast Fourier Transform (RFFT) Architecture with Carry Increment and Pipelined Adders

Correction to: Chapter “Design of High Speed Approximate Carry Select Adders Using RCPFA” in: T. Sengodan et al. (eds.), Advances in Electrical and Computer Technologies, Lecture Notes in Electrical Engineering 881, https://doi.org/10.1007/978-981-19-1111-8_58 

/pdf/correction-to-design-of-high-speed-approximate-carry-select-1ml316ba.pdf

Rajasekhar Turaka

Papers

Design of approximate reverse carry select adder using RCPA

Low power VLSI implementation of real fast Fourier transform with DRAM-VM-CLA

Low-Complexity High Speed Memory Based Real Fast Fourier Transform (RFFT) Architecture with Carry Increment and Pipelined Adders

Correction to: Design of High Speed Approximate Carry Select Adders Using RCPFA

A novel approach for design energy efficient inexact reverse carry select adders for IoT applications