SIS is an interactive tool for synthesis and optimization of sequential circuits Given a state transition table, a signal transition graph, or a logic-level description of a sequential circuit, it produces an optimized net-list in the target technology while preserving the sequential input-output behavior Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process It is built on top of MISII [5] and includes all (combinational) optimization techniques therein as well as many enhancements SIS serves as both a framework within which various algorithms can be tested and compared, and as a tool for automatic synthesis and optimization of sequential circuits This paper provides an overview of SIS The first part contains descriptions of the input specification, STG (state transition graph) manipulation, new logic optimization and verification algorithms, ASTG (asynchronous signal transition graph) manipulation, and synthesis for PGA’s (programmable gate arrays) The second part contains a tutorial example illustrating the design process using SIS

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SIS : A System for Sequential Circuit Synthesis

From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. In the past few years, a number of heuristic algorithms have been proposed for technology mapping in lookup-table (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Boolean networks and little is known about how far their solutions are away from the optimal ones. This paper presents a theoretical breakthrough which shows that the LUT-based FPGA technology mapping problem for depth minimization can be solved optimally in polynomial time. A key step in our algorithm is to compute a minimum height K-feasible cut in a network, which is solved optimally in polynomial time based on network flow computation. Our algorithm also effectively minimizes the number of LUT's by maximizing the volume of each cut and by several post-processing operations. Based on these results, we have implemented an LUT-based FPGA mapping package called FlowMap. We have tested FlowMap on a large set of benchmark examples and compared it with other LUT-based FPGA mapping algorithms for delay optimization, including Chortle-d, MIS-pga-delay, and DAG-Map. FlowMap reduces the LUT network depth by up to 7% and reduces the number of LUT's by up to 50% compared to the three previous methods. >

/pdf/flowmap-an-optimal-technology-mapping-algorithm-for-delay-59gk35bj0r.pdf

FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

Recent directions in netlist partitioning: a survey

Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical, and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

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Power minimization in IC design: principles and applications

The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architecture: table-lookup and multiplexer-based. The constraints imposed by some of these architectures require new algorithms for minimization of the number of basic blocks of the target architecture, taking into account the wiring resources. The presented algorithms are general and can be used for both of the above-mentioned architectures. >

Logic synthesis for programmable gate arrays

The authors address the problem of synthesis for a popular class of programmable gate array architecture-the table look-up architectures. These use lookup table memories to implement logic functions. The authors present improved techniques for minimizing the number of table look up blocks used to implement a combinational circuit. On average, the results obtained on a set of benchmarks are 15-29% better than results obtained by previous approaches. >

https://www.computer.org/csdl/pds/api/csdl/proceedings/download-article/12OmNAPSMnF/pdf

Improved logic synthesis algorithms for table look up architectures

The authors address the problem of delay optimization for programmable gate arrays. The main considerations are the number of levels in the circuit and the wiring delay. The authors propose a two-phase approach: the first phase involves delay optimizations during logic synthesis before placement, while the second uses logic resynthesis in the case of a timing-driven placement technique. Results and comparisons on benchmarks are presented. >

Performance directed synthesis for table look up programmable gate arrays

The authors address the problem of clustering a circuit for minimizing its delay, subject to capacity constraints on the clusters. They present an algorithm for combinational circuits and give sufficient conditions under which it is optimum. In addition, they address the problem of minimizing the number of clusters and nodes without increasing the maximum delay found by the algorithm. Finally, they extend the clustering algorithm to minimize the clock cycle of a sequential synchronous circuit. >

On clustering for minimum delay/ara

In one embodiment, a method for crosstalk-aware timing analysis includes accessing a design of a circuit and identifying critical paths in the design. Each critical path includes one or more victim interconnects and one or more cells. The method includes identifying potential aggressor interconnects associated with each victim interconnect and, for each victim interconnect, extracting parasitics of the victim interconnect and the potential aggressor interconnects associated with the victim interconnect. The method includes computing timing windows of the potential aggressor interconnects and computing a first timing of each cell and each victim interconnect on each critical path. The method also includes, for each critical path, generating timing waveforms of the potential aggressor interconnects, traversing the critical path from a start point on the critical path to an end point on the critical path, and, computing a second timing of each cell and each victim interconnect on the critical path according to a traversal of the critical path.

Rajeev Murgai

Papers

Logic synthesis for programmable gate arrays

Improved logic synthesis algorithms for table look up architectures

Performance directed synthesis for table look up programmable gate arrays

On clustering for minimum delay/ara

Crosstalk-aware timing analysis