Programmable logic arrays (PLA's) are extensively used to realize area efficient combinational logic circuits. As the size of the PLA's increases, a cost-effective way to test them is to realize testable PLA's. In this paper a new approach to the design of testable PLA's is presented. The proposed method leads to testable PLA's with minimal area penalty and small number of tests that can be obtained as a by-product of the synthesis procedure, or can be directly obtained from the personality of the PLA's, thus simplifying the test derivation step. Results of an experiment involving 56 PLA's, to compare the test set sizes of differenit testable PLA designs (including the design proposed here) as well as the size of tests derived to detect single faults by algorithmic procedures are also reported.

A New Approach to the Design of Testable PLA's

(2m± 1) [HGS83b]. (d, k) [MR82]. (N,K) [KK86]. 1 [wu87b]. 1/2 [ZW87]. 2 [FLN89, Jes80a, KR82, RY82]. 2(log2N)− 1 [Lee85b]. 2/3 [ZW87]. 22n+ 1 [STR87]. 2m [PNH88]. 3 [WH88]. 4 [KW81, TPSS85]. 5.8n log2 n [CW80]. 8 [Kal83]. [lgN + 1] [CT84a]. 2 [DD81, Eti80, FM89]. 2.5 [DM84]. p [SLS82]. n [HSE84]. AB [Bla83, Slo85]. D [Kak85, Kak83, LB88, SW82, WV87, WR81]. d > t [LB88]. ` [Hoc83]. GF (2) [Fen89, WTS85, YRT84, Zho88]. GF (P ) [TKL86, HQR89]. GF [p] [Eng81]. K [GM87, NHAT89, Agg86, BL84, CI88, CE87, Dav89, Lee82, LC87b]. L/U [JK82]. λT [CGMP87]. M [Bla83, Mor80, Slo85, WH80a, Wus81, GH83b, HGS83b, PNH88]. m2 [MM83a]. N [CS87, Er84, Esf89, Mor80, Wus81, AP89, AG81b, Bha83a, GH83b, Kha82, LM87a]. n− 1/n [Nil84, Wen85, Can83]. O(2) [Jia86]. O(log n) [BP85]. O(n) [Sip82]. O(n+ k) [LD88]. O(N/ log N) [SR81a]. O(t + |E|) [Sul88]. P [Tha82, Tha84b, TKL86, YF88, Fro83, GNK86, KM83b, Wus82]. r [GH83a, HGS83a]. s [SSS89]. t [BV89, CA89, LB88, NGP86].

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A Bibliography of IEEE Transactions on Computers (1980{1989)

For Part I, see 2nd NASA/DoD Workshop on Evolvable Hardware, pp.183-193 (July 2000). Describes an advanced self-testing, self-repair architecture and methodology for Lattice Logic Corp.'s GAL (generic array logic) devices, which are EPLDs (electrically programmable logic devices) that are used in high-security and safety applications, such as aerospace systems, military systems or medical instruments. We describe a new "column re-use" method that, if possible, exchanges a faulty GAL column with a column that needs the same programming as supplied by the faulty column and then reprograms the freed column to replace the faulty one. In contrast, our former self-repairing methodology, called the "column replacement method with extra columns", described Part I, just discarded each faulty column and replaced it with an extra column. Our evaluation methodology shows that the lifetime of a GAL that uses the 'column re-use' method is longer than the lifetime of a GAL that uses just the 'column replacement' method or the 'no self-repair' method. Our results also give information on how many extra columns a GAL needs to reach a lifetime goal, in terms of the simulation looping time, until the GAL is not useful any more. Our system is also applicable to other devices, such as FPGAs (field programmable gate arrays).

https://ieeexplore.ieee.org/iel5/7440/20223/00934448.pdf

Self-repairable EPLDs. II. Advanced self-repairing methodology

This paper describes the concept of self-testable and self-repairable EPLDs (Electrically Programmable Logic Devices) for high security and safety applications. A design methodology is proposed for self-repairing of a GAL (Generic Array Logic) which is a kind of EPLD. Our fault-locating and fault-repairing architecture uses universal test sets, fault-detecting logic, and self-repairing circuits with spare devices. The design method allows to detect, diagnose, and repair all multiple stuck-at faults which might occur on E/sup 2/CMOS cells in programmable AND plane. A "column replacement" method with extra columns is introduced that discards each faulty column entirely and replaces it with an extra column. The evaluation methodology proves that the self-repairable GAL will last longer in the field.

Self-repairable EPLDs: design, self-repair, and evaluation methodology

The fault equivalence problem in programmable logic arrays (PLAs) is introduced. Some design rules are proposed. Based on the pseudoexhaustive testable PLA structure, a diagnosis algorithm was developed and implemented on a SUN 3/110 workstation in C language. Experimental results show that this design and the algorithm are quite efficient for PLA fault diagnosis. >

A new design to prevent fault equivalence in PLAs

An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA). The main feature of the algorithm is the determination of a fault set corresponding to the response obtained for a failed test. For the apparently small number of faults in this set, all other tests are generated and a fault table is formed. Subsequently, an adaptive procedure is used to diagnose the fault. Functional equivalence test is carried out to determine the actual fault class if the adaptive testing results in a set of faults with identical tests. The large amount of computation time and storage required in the determination, a priori, of all the fault equivalence classes or in the construction of a fault dictionary are not needed here. A brief study of functional equivalence among the cross point faults is also made.

Ramanatha

Papers

An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays