In this paper, we present the design, fabrication, and measurement of an ultra-wideband phased array antenna, with continuous coverage of all six allocated fifth generation and industrial, scientific, medical bands in the millimeter-wave spectrum. Of importance is that the complete array is co-fabricated as a single printed circuit board using commercial processes, implying a significant reduction in cost over previous microfabrication-based designs. The design is demonstrated in simulation to operate across 24–72 GHz with VSWR $3\times 3$ array prototype, which shows close agreement to the simulated values.

Ultra-Wideband Phased Array for Millimeter-Wave ISM and 5G Bands, Realized in PCB

This paper investigates design considerations and challenges of integrating on-chip antennas in nanoscale CMOS technology at millimeter-wave (mm-wave) to achieve a compact front-end receiver for 5G communication systems. Solutions to overcome these challenges are offered and realized in digital 28-nm CMOS. A monolithic on-chip antenna is designed and optimized in the presence of rigorous metal density rules and other back-end-of-the-line (BEoL) challenges of the nanoscale technology. The proposed antenna structure further exploits ground metallization on a PCB board acting as a reflector to increase its radiation efficiency and power gain by 37.3% and 9.8 dB, respectively, while decreasing the silicon area up to 30% compared to the previous works. The antenna is directly matched to a two-stage low noise amplifier (LNA) in a synergetic way as to give rise to an active integrated antenna (AIA) in order to avoid additional matching or interconnect losses. The LNA is followed by a double-balanced folded Gilbert cell mixer, which produces a lower intermediate frequency (IF) such that no probing is required for measurements. The measured total gain of the AIA is 14 dBi. Its total core area is 0.83 mm
 2
 while the total chip area, including the pad frame, is 1.55 × 0.85 mm
 2
.

/pdf/challenges-in-on-chip-antenna-design-and-integration-with-rf-872an50q2l.pdf

Challenges in On-Chip Antenna Design and Integration with RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems

With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs) will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave) wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC) and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

To meet the growing demand for miniaturization and compactness, antennas are being designed over CMOS chips. On-chip antennas (OCAs) suffer from low gains and radiation efficiency due to high dielectric constant and low resistivity of Silicon. Artificial magnetic conductors (AMC) are used in OCAs to increase gain and reduce power confinement in the substrate. In this paper, a bowtie slot antenna is presented whose gain is enhanced by an array of back-to-back E-shaped (B2BE) frequency selective surface (FSS). The operating frequency of antenna is 94 GHz where its gain is boosted from −2.71 dBi to −1.94 dBi. Designed in a standard IHP 130nm BiCMOS process without any extra post-processing step, the S11 is below −10dB from 90 GHz to 105 GHz with an antenna size of 710×310×650 µm3

Design of bowtie-slot on-chip antenna backed with E-shaped FSS at 94 GHz

This paper presents a small size 60 GHz Antenna-on-Chip (AoC) designed and fabricated using 0.18 um TSMC Complementary Metal Oxide Semiconductor (CMOS) process. AoC performance is enhanced using asymmetric Artificial Magnetic Conductor (AMC). The AoC area including the AMC is 1715 um by 710 um. As AMC shields AoC from the lossy CMOS substrate, simulated gain of -0.25 dBi is achieved at 60 GHz for design rule compatible circular AoC with 12.8 dB front-to-back ratio (FBR) due to removal of AMC cells below the AoC. Measurements agree well with simulation results and confirm operation at the 60 GHz band with a peak measured gain of -3 dBi at 64 GHz.

Small size 60 GHz CMOS Antenna-on-Chip: Gain and efficiency enhancement using asymmetric Artificial Magnetic Conductor

This paper presents an optimization methodology for a 60 GHz triangular monopole Antenna-on-Chip (AOC), designed using a standard 0.18 µm CMOS process and optimized over a Jerusalem Cross Artificial Magnetic Conductor (JC-AMC). The JC-AMC acts as a shield between the AOC and the lossy CMOS substrate. Different configurations of JC-AMC cells are tested to acquire best AOC performance. It has been found that increasing the number of JC-AMC cells in the feeding direction and decreasing its number of cells in the direction perpendicular to the feed can improve the antenna characteristics in terms of gain, efficiency, front-to-back ratio, and small area.

Performance optimization of a 60 GHz Antenna-on-Chip over an Artificial Magnetic Conductor

A high-gain and small-area triangular monopole Antenna-on-Chip (AOC), designed using a standard CMOS process and optimized over a modified rectangular Artificial Magnetic Conductor (AMC). The rectangular AMC acts as a shield between the AOC and the lossy CMOS substrate. Using this configuration, a Frequency Selective Surface (FSS) is realized by the shield providing high wave impedance around 60 GHz. The AOC dimensions including the AMC are 0.86 mm by 1.76mm. The antenna gain is 0.3 to 1 dBi from 57 to 64 GHz.

60 GHz triangular monopole Antenna-on-Chip over an Artificial Magnetic Conductor

This paper presents a 60 GHz Antenna-on-Chip (AoC) designed using 0.18µm CMOS process. AoC performance is enhanced using asymmetric Artificial Magnetic Conductor (AMC). As asymmetric AMC shields AoC from the lossy CMOS substrate, gain and efficiency of 0.8dBi and 49%, respectively, are achieved. Asymmetric AMC has similar properties to the conventional Perfect Electric Conductor (PEC) allowing for reduced feeding circuit loss than symmetric AMCs. The asymmetric AMC saves about 2dB/mm at 60GHz of insertion loss than symmetric AMC. Keyword 60 GHz, CMOS, Antenna-on-Chip (AoC), Artificial Magnetic Conductor (AMC) The 60 GHz band is known by its unlicensed wide bandwidth of 7 GHz (from 57 to 64 GHz) which allows for data rates of several gigabytes, surpassin g current technologies. AoC is a promising technology that guarantees single chip integration of the antenna, radio frequency circuits and digital circuits allowing for System-on-Chip (SoC), hence, promising low cost and power saving devices. However, the CMOS substrate inherited losses due to its high permittivity and low resistivity causes performance degradation (1). Design methodologies such as micromachining (2) and proton implantation (3) are used to improve the AoC performance. Nevertheless, these techniques reduce system level integration and increase the overall cost.

Ramesh K. Pokharel

Papers

Performance optimization of a 60 GHz Antenna-on-Chip over an Artificial Magnetic Conductor

60 GHz triangular monopole Antenna-on-Chip over an Artificial Magnetic Conductor

60 GHz Antenna-on-Chip (AoC) using Asymmetric Artificial Magnetic Conductor (AMC) on 0.18 m CMOS technology