A high-performance, resource-efficient, reconfigurable parallel-pipelined FFT processor for FPGA platforms

While computer vision tasks target increasingly challenging scenarios, the need for real-time processing of images rises as well, requiring more efficient methods to accelerate convolutional neural networks For unit stride convolutions, we use FFT-based methods and Winograd algorithms to compute matrix convolutions, which effectively lower the computing complexity by reducing the number of multiplications For non-unit stride convolutions, we usually cannot directly apply those algorithms to accelerate the computations In this work, we propose a novel universal approach to construct the non-unit stride convolution algorithms for any given stride and filter sizes from Winograd algorithms Specifically, we first demonstrate the steps to decompose an arbitrary convolutional kernel and apply the Winograd algorithms separately to compute non-unit stride convolutions We then present the derivation of this method and proof by construction to confirm the validity of this approach Finally, we discuss the minimum number of multiplications and additions necessary for the non-unit stride convolutions and evaluate the performance of the decomposed Winograd algorithms From our analysis of the computational complexity, the new approach can benefit from 15x to 3x fewer multiplications In our experiments in real DNN layers, we have acquired around 13x speedup (T old / T new ) of the Winograd algorithms against the conventional convolution algorithm in various experiment settings

Accelerate Non-unit Stride Convolutions with Winograd Algorithms

Filter bank multi-carrier (FBMC) is the candidate modulation technique for the next generation of wireless networks (5G) as it provides a better spectral efficiency with little intersymbol interference (ISI) and intercarrier interference (ICI). Unfortunately, FBMC architecture has a complex structure; a large number of multipliers, adders, and subtractors are needed to implement fast fourier transform (FFT) and finite impulse response (FIR) components, which causes a high-power consumption and reduce the speed of the entire system especially in case of a large number of subscribers. This paper presents a complete design and implementation of a proposed low power FBMC transceiver architecture for a different number of multi-users or subscribers. The suggested method aims to reduce power consumption and area resources through reducing the complexity of the FFT (2n Points) processor by using a feedback loop with a (n) points FFT core. Also, the design of FIR filters is based on distributed arithmetic (DA) algorithm in which all multiplications and additions are replaced by a table and a shifter. The design and implementation are done using a Xilinx system generator tool and spartan-6 field programmable gate array (FPGA) board. The proposed implementation method presents a reduction in resources by 15 % compared to conventional implementation.

Low Power Implementation of FBMC Transceiver for 5G Wireless Networks

LAPAN-A3/IPB multispectral imager has the ability to produce realtime acquisition images anywhere in the world as long as there is X-band receiver in ground station to receive the image data. The received image data is the compressed version of the original image data, compressed by lossy algorithm of Fast-Fourier Transform and Huffman encoding. Processing of the received image data can be considered complicated in terms of decompressed image data validity and processing time needed. This research aims to develop robust decoding algorithm for LAPAN-A3/IPB multispectral image received in realtime acquisition mode from Bogor ground station. The research focuses on developing efficient method on Huffman decoding for relatively big image data by using look-up-table approach. The developed decoding algorithm has successfully produced daily LAPAN-A3/IPB realtime images with good image quality, where the results have been validated by using original images, recorded on satellite memory. However, the time processing needed for processing any single image is still poor, where 1 GB of compressed image data needs around 1 hour of processing time. Therefore, although the algorithm has been used to regularly produce daily LAPAN-A3/IPB realtime image data, the faster algorithm is needed to achieve better overall processing performance.

Huffman decoding performance analysis of lossy compressed LAPAN-A3/IPB multispectral images

Real-Time Parallel Processing of Vibration Signals Using FPGA Technology

The Fast Fourier Transform is one of the most widely used digital signal processing algorithms. It is used to compute the Discrete Fourier Transform and its inverse. As a result, these are widely used for many applications in engineering, science, and mathematics which include areas such as: communications, signal processing, instrumentation, biomedical engineering, numerical methods, sonics and acoustics, and applied mechanics. It is described as the most important numerical algorithm of our lifetime. The number of applications for this transform continues to grow. The Decimation-In-Time radix-2 FFT using butterflies is designed. The butterfly operation is faster. The outputs of the shorter transforms are reused to compute many outputs, thus the total computational cost becomes less. The 16 bit and 32 bit inputs are synthesized using Verilog. The logic utilization obtained from the design summary of 16 and 32 bit radix-2 DIT FFT can be compared. The utilization factor increases as the number of bits increases. The design is developed using hardware description language Verilog on Xilinx 14.2 xc3s500E. The spartan3-tyro plus is used as hardware to implement the complex FFT values.

Remya Ramachandran

Papers

FPGA implementation of Fast Fourier Transform