R
Richard M. Fujimoto
Researcher at Georgia Institute of Technology
Publications - 290
Citations - 13908
Richard M. Fujimoto is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Discrete event simulation & Network simulation. The author has an hindex of 52, co-authored 290 publications receiving 13584 citations. Previous affiliations of Richard M. Fujimoto include Mitre Corporation & University of Colorado Colorado Springs.
Papers
More filters
Proceedings ArticleDOI
Time management in the DoD high level architecture
TL;DR: The time management component of the HLA that defines the means by which individual simulations (called federates) advance through time is described, to support interoperability among federates using different local time management mechanisms.
Book ChapterDOI
On synthesizing systolic arrays from recurrence equations with linear dependencies
TL;DR: A simple test consisting of finding the zeroes of a matrix is sufficient to determine whether a systolic array can be derived if the communication can be spatially and temporally localized and give a construction that generates the array when such a pipelining is possible.
Proceedings ArticleDOI
A case study in simulating PCS networks using Time Warp
TL;DR: Experiences in developing two PCS simulation models on a general purpose distributed simulation platform based on the Time Warp mechanism indicate that the high locality in large-scale PCS network simulations make them well-suited for execution on general purpose parallel and distributed simulation platforms.
Journal ArticleDOI
Parallel simulation techniques for large-scale networks
TL;DR: Based on the accumulated experience in parallel network simulation projects, it is believed that parallel simulation technology has matured to the point that it is ready to be used in industrial practice of network simulation.
Proceedings ArticleDOI
The virtual time machine
TL;DR: This paper outlines the motivations behind the VTM architecture, the underlying computation model, a proposed implementation, and initial performance results, and argues that this architectural deficiency is the underlying reason behind many difficult problems in parallel computation today.