A gateway for screening packets transferred over a network. The gateway includes a plurality of network interfaces, a memory and a memory controller. Each network interface receives and forwards messages from a network through the gateway. The memory temporarily stores packets received from a network. The memory controller couples each of the network interfaces and is configured to coordinate the transfer of received packets to and from the memory using a memory bus. The gateway includes a firewall engine coupled to the memory bus. The firewall engine is operable to retrieve packets from the memory and screen each packet prior to forwarding a given packet through the gateway and out an appropriate network interface. A local bus is coupled between the firewall engine and the memory providing a second path for retrieving packets from memory when the memory bus is busy.

Firewall including local bus

A computer system includes a microprocessor that is electrically connected to a first synchronous bus operating in synchronism with a first clock signal at a first clock frequency. A second synchronous bus operates in synchronism with a second clock signal at a second clock frequency and provides electrical communication to a number of peripheral devices. An asynchronous bus provides data communication between the first and second synchronous bus using handshaking signals so that the first and second clock signals operate independently of each other. The operating frequency and other parameters of the microprocessor and the first synchronous bus can be changed without requiring any changes to the second synchronous bus so that the microprocessor and the first synchronous bus can take advantage of advances in technology while allowing the second synchronous bus and the associated peripheral devices to remain compatible with previous versions of the computer system.

Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus

An integrated circuit chip that facilitates connecting peripheral devices to an MCA Micro Channel Architecture bus system. With the present invention manufacturers of adapter boards and cards can easily interface peripheral devices to an MCA bus. With the present invention the MCA interface is segmented in a different manner than it is segmented in prior art adapters. In the approach utilized with the present invention the interface has been partitioned so that the microchannel signals and the protocol signals common to all functions are contained on an interface chip. The present interface integrated chip combines (a) command decode circuitry for receiving coded signals from the MCA bus and for generating decoded command signals for peripheral devices, (b) pin control circuitry which controls multi-function pins, (c) bus arbitration control circuitry, (d) POS Programmable Option Select register control circuitry to facilitate adapter identification support, (e) ready logic circuitry to facilitate synchronous ready signal generation, (f) circuitry to facilitate device error reporting, (g) external data buffer control, (h) bus response signal generation circuitry, and (j) circuitry to support memory and I-O relocation. The above combination of functions is provided on a single integrated circuit thereby efficiently utilizing the limited number of I-O pins available on the integrated circuit.

Personal computer bus interface chip with multi-function address relocation pins

An information processing system comprises a high speed noninterlocked system bus 12 which couples together a plurality of system units including a main memory and a system bus interface (SBI) unit 34. The system bus interface unit is further coupled to an I/O bus 42 having a plurallity of I/O Processors 44, 46 coupled thereto. The system bus interface includes read and write buffer storage for buffering information units being transferred between the system bus and the I/O bus. The I/O bus includes two signal lines which differentiate the condition of an I/O bus SBI BUSY signal line. One of these two signal lines indicates when the SBI read buffer is full while the other signal line indicates when the SBI write buffer is full. The SBI Busy signal line indicates when either of these conditions exist. I/O processors are enabled to differentiate between read and write buffer full conditions, thereby effectively increasing the bandwidth of the I/O bus.

Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus

An I/O structure for use in a digital data processing system of the type in which system components including a processor and a system memory are connected by a system bus. The I/O structure includes a system bus interface connected to the system bus, a synchronous satellite processing unit (SPU) bus connected to the system bus interface, one or more satellite processing units (SPUs) connected to the SPU bus, and peripheral devices attached to the satellite processing units. Each SPU has three main components: control logic including a microprocessor for controlling the SPU, a device adapter specific to the peripheral device for controlling the peripheral device and transferring data between the peripheral device and the SPU, and an interface unit connected to the control logic and the device adapter for providing I/O communications to the SPU bus and responding to I/O communications on the SPU bus. The I/O communications fall into two classes: communications to SPUs and communications to system components. The communications to SPUs all require a single SPU bus cycle; the communications to system components require one or more cycles. The system bus interface translates communications to system components into communications on the system bus and translates communications on the system bus intended for a SPU into communications to SPUs. The SPU bus includes first lines for carrying an I/O command and an identifier for an SPU involved in the communication and second lines for carrying the contents of the communication. In multicycle communications, the I/O command and identifier remain on the first lines for all cycles, but the information on the second lines varies from cycle to cycle.

I/O structure for information processing system

An asynchronous interface adapter for interfacing two bidirectional data buses. Data transfer between buses may occur simultaneously with provision made for storing bus data from a first bus until a receiver on the second bus is available. The adapter provides bus requests and grant logic, parity checking, time of day clocking, and is adapted to handle variable-length bus messages with the message bytes being carried in a bit-parallel byte-serial form, asynchronously and generally in a bidirectional manner.

Richard S. Grau

Papers

Adapter for interfacing between two buses