Riichiro Shirota

TL;DR: In this article, an erasable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate, each of which has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain.

TL;DR: In this paper, a sense amplifier is connected to bit lines and a comparator is used to compare the actual data read from one of the programmed cell transistors with the write-data, to verify its written state.

TL;DR: A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area, a gate wiring stack body formed on the cell array, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on a side surface of the gate wires stack body, where an insulating charge storage layer is contained as mentioned in this paper.

TL;DR: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a multiplicative memory cells in an intersecting plane share the first gate electrode as discussed by the authors.

Abstract: A nonvolatile semiconductor memory of an aspect of the present invention comprises a semiconductor substrate, a pillar-shaped semiconductor layer extending in the vertical direction with respect to the surface of the semiconductor substrate, a plurality of memory cells arranged in the vertical direction on the side surface of the semiconductor layer and having a charge storage layer and a control gate electrode, a first select gate transistor arranged on the semiconductor layer at an end of the memory cells on the side of the semiconductor substrate, and a second select gate transistor arranged on the semiconductor layer on the other end of the memory cells opposite to the side of the semiconductor substrate, wherein the first select gate transistor includes a diffusion layer in the semiconductor substrate and is electrically connected to the pillar-shaped semiconductor layer by way of the diffusion layer that serves as the drain region.