A multi-streaming processor (14) has multiple streams (4) for processing multiple threads (1-3), and an instruction scheduler (5) including a priority record of priority codes (7, 8) for one or more of the streams (4). The priority codes (7, 8) determine in some embodiments relative access to resources (10-13) as well as which stream (4) has access at any point in time. In other embodiments priorities are determined dynamically and altered on-the-fly, which may be done by various criteria, such as on-chip processing statistics, by executing one or more priority algorithms, by input from off-chip (9), according to stream loading, or by combinations of these and other methods. In one embodiment a special code is used for disabling a stream, and streams may be enabled and disabled dynamically by various methods, such as by on-chip events, processing statistics, input from off-chip, and by processor interrupts. Some specific applications are taught, including for IP-routers and digital signal processors.

Prioritized instruction scheduling for multi-streaming processors

A technique for dynamically exploiting affinity, locality, and load balancing in scheduling the execution of multi-threaded user programs in a multi-processor computer system. Affinity, locality, and load balancing characteristics are specified at thread creation time and can be dynamically changed during thread execution, either by the user program itself or by any other process or entity with sufficient privileges and information. A central schedule queue and one or more per-processor local schedule queues are used to schedule the threads based on the dynamically changing affinity, locality, and load balancing characteristics.

Affinity, locality, and load balancing in scheduling user program-level threads for execution by a computer system

A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit operable to combine the plurality of instruction streams into a serial instruction stream, and a distribution unit operable to distribute the serial instruction stream to an array of processing elements.

Parallel data processing apparatus

A system and method for providing IP services. A packet is received at a line interface/network module and forwarded to a virtual routing engine The virtual routing engine determines if the packet requires processing by a virtual services engine. If the packet requires processing by the virtual services engine, the packet is routed to the virtual services engine for processing.

Service processing switch

A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting another stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, and thereby may exert any and all available control mechanisms relative to other streams without interference by any stream. Supervisory modes are taught as well, wherein control may be granted from minimal to full control, with compliance of controlled streams, which may alter or withdraw control privileges. Various mechanisms are disclosed, including a mechanism wherein master status and interstream control hierarchy is recorded and amended by at least one on-chip bit map. In this mechanism each stream maintains and edits a bitmap granting or withdrawing control privileges for each other stream, the settings valid for any stream but a Master stream, which will ignore the settings.

Interstream control and communications for multi-streaming digital processors

Closely related processing threads within a process in a multiprocessor system are collected into thread groups which are globally scheduled as a group based on the thread group structure's priority and scheduling parameters. The thread group structure maintains collective timeslice and CPU accounting for all threads in the group. Within each thread group, each individual thread has a local scheduling priority for scheduling among the threads in its group. The system utilizes a hierarchy of processing levels and run queues to facilitate affining thread groups with processors or groups of processors when possible. The system will tend to balance out the workload among system processors and will migrate threads groups up and down through processing levels to increase cache hits and overall performance. The system is periodically reset to avoid long term unbalanced operation conditions.

Robert A. Alfieri

Papers

Apparatus and method for improved CPU affinity in a multiprocessor system