A zero-drift analog memory (ZDAM) cell that indefinitely maintains an output signal at a discrete voltage while the memory circuit is powered, wherein the memory circuit receives an input signal, passes the input signal to a storage element upon receiving an assertion signal, maintains an output signal at a level of the input signal when the assertion signal is removed, and utilizes a zero-drift transfer function feedback loop on the output signal to maintain the output signal. A memory array including a plurality of ZDAM cells and method of operation are also disclosed.

Zero drift analog memory cell, array and method of operation

A pulse delivery control signal is applied to and removed from a master or pulse delivery electronic switch to respectively start and terminate the delivery of a trapezoidal waveform defibrillation pulse from charge storage capacitors to a patient. In one specific embodiment, a transfer charge storage circuit is coupled to a capacitor charging circuit for charging as the charge storage capacitors are charged. A transfer switch interconnects the transfer charge storage circuit to a first field-effect transistor switch. In response to a transfer signal, a transfer voltage signal is delivered from the transfer charge storage circuit, through the transfer switch and to the first field-effect transistor. In response, the first field-signal transistor applied the pulse delivery control signal to the master switch. A second field-effect transistor may be included for operating the master switch together with the first field-effect transistor. Voltage detection and energy selection circuits may be employed for detecting when the charge storage capacitors in the circuit are charged to a desired level and for establishing the level to which the capacitors are charged to thereby control the energy delivered by the defibrillation pulses.

Defibrillator circuit for producing a trapezoidal defibrillation pulse

A circuit for maintaining the level of an output signal at a value which is essentially equal to the value of a periodically sampled input signal, said circuit including a pair of gates which are made simultaneously conductive over a controlled sampling time interval whereby an input signal is applied to a storage device which thereupon produces an output signal, the level of which is maintained for a particular time period at the level of the sampled input signal

Sample and hold circuit

An examination answer sheet, on which the examinee has darkened certain discrete areas with a graphite or lead pencil to denote his selected answers to multiple choice questions, is moved relative to a plurality of photoelectric cells, these cells providing analog voltages having magnitudes in accordance with the opacity of the marks or data on the sheet. During time intervals derived photoelectrically from a sequence of marks constituting a timing track, the highest voltages provided by the data cells are individually stored, later digitized, and the digital information forwarded to a computer for comparative processing with answer information contained in the computer's memory.

Apparatus utilizing analog-to-digital conversion in the photoelectric reading of documents

The invention concerns a sample and hold circuit including charge storage capacitors and switches connected between input and output amplifiers and operable to provide substantially improved isolation of a hold capacitor from the input amplifier, as during the hold period, and also to provide compensation for the transient jump in voltage developed at the hold capacitor during switching.

Robert C Bedingfield

Papers

Sample and hold circuit using an operational amplifier and a high impedance buffer connected by a switched diode capacitor circuit

Trapezoidal test signal generator with leading and trailing edge control