A system, method, and computer program product are provided for a touch or pressure signal-based interface. In operation, a touch or pressure signal is received in association with a touch interface of a device. To this end, a user experience is altered utilizing the signal. A system, method, and computer program product are provided for modifying one or more objects in one or more memory devices. In one embodiment, an apparatus is provided, comprising one or more memory devices including a non-volatile memory. Additionally, the apparatus comprises circuitry including a first communication path for communicating with the at least one processor, and a second communication path for communicating with at least one storage sub-system which operates slower than the one or more memory devices. Further, the circuitry is operable to modify one or more objects in the one or more memory devices.

User interface system, method, and computer program product

Described is a technology by which a memory controller is a component of a hybrid memory device having different types of memory therein (e.g., SDRAM and flash memory), in which the controller operates such that the memory device has only a single memory interface with respect to voltage and access protocols defined for one type of memory. For example, the controller allows a memory device with a standard SDRAM interface to provide access to both SDRAM and non-volatile memory with the non-volatile memory overlaid in one or more designated blocks of the volatile memory address space (or vice-versa). A command protocol maps memory pages to the volatile memory interface address space, for example, permitting a single pin compatible multi-chip package to replace an existing volatile memory device in any computing device that wants to provide non-volatile storage, while only requiring software changes to the device to access the flash.

Hybrid memory device with single interface

An apparatus is provided comprising a physical memory sub-system including a first memory of a first memory class and a second memory of a second memory class, the second memory being communicatively coupled to the first memory. The apparatus is configured such that the first memory and the second memory are capable of receiving instructions via the memory bus. A system and method are also provided for circuit cooperation. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit. Furthermore, the system is operable such that the at least one first circuit and the at least one additional circuit cooperate to carry out at least one task.

Multiple class memory systems

A battery detect circuit (32) is connected to the battery with the current input to the battery and extracted from the battery measured with a sense resistor (50) and then converted to charge and discharge pulses with a V/F converter (52) A microcontroller (64) is operable to increment a Nominal Available Charge (NAC) register (180) during a charge operation, and to increment a Discharge Count Register (DCR) (184) during a discharge operation The NAC register (180) indicates the available charge, which value is output to a display (34) The maximum value to which the NAC value can rise is limited by a value stored in the last measured discharge register (182) This value represents the value stored in the DCR (184) whenever the battery is discharged from an apparent full state to a fully discharged state This results in a qualified transfer to the LMD register (182) such that no knowledge of the actual battery charge is necessary The charge rate is varied as both a function of temperature, voltage and also of the state of charge A fast charge rate is initiated when the charge state is above a predetermined low voltage threshold and less than full When the charge state reaches a level within approximately 80% of full charge, the charge rate is reduced At full capacity, the charge rate is further reduced to a top off charge rate which continues for approximately two hours If the temperature falls below a predetermined low temperature threshold, the charge rate is again reduced to a safe, slow, effective rate Trickle charge is provided to replenish charge adaptively in accordance with a self-discharge counter The trickle charge operates to momentarily pulse the battery (10) at a predetermined charge rate

Method and apparatus for monitoring batttery capacity with charge control

An embedded ROM has a column of static RAM cells attached to the end of the row lines. When a row of ROM cells is activated by the row line, a RAM cell is also activated by the row line. The RAM cell indicates if the data in the selected row's ROM cells is valid. When the RAM cell indicates that the ROM data is not valid, external memory is read to obtain a patched instruction and the ROM data is ignored. The ROM's base address is translated to a base address in external memory of patch code. The ROM's offset address is used as the offset into the patch-code region of external memory. Thus address translation is minimal as the offset is not translated. A single ROM instruction can be updated by a single patch instruction in external memory, providing fine granularity of code updates. Longer update routines can be located in a patch-code overflow region of external memory. The updated instruction at the ROM's offset in the patch-code region can be a jump instruction to the longer update routine in the overflow region. Thus both single and multiple-instruction patches are possible.

Embedded rom with ram valid bits for fetching rom-code updates from external memory

An integrated circuit memory which includes at least some RAM/ROM hybrid columns. The RAM/ROM hybrid cells operate as normal SRAM cells forever, unless and until they are programmed to operate as ROM cells. Thus users who need the extra security permitted by ROM encoding can have this capability, while users who do not need ROM encoding can use off-the-shelf parts as RAM only.

Ram/ROM hybrid memory architecture

An integrated circuit memory which includes at least some RAM/ROM hybrid columns The RAM/ROM hybrid cells operate as normal SRAM cells forever, unless and until they are programmed to operate as ROM cells Thus users who need the extra security permitted by ROM encoding can have this capability, while users who do not need ROM encoding can use off-the-shelf parts as RAM only

Robert D. Lee

Papers

Ram/ROM hybrid memory architecture

Programmable memory and cell