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Robert Ecoffet

Researcher at Centre National D'Etudes Spatiales

Publications -  173
Citations -  2805

Robert Ecoffet is an academic researcher from Centre National D'Etudes Spatiales. The author has contributed to research in topics: Single event upset & Engineering. The author has an hindex of 27, co-authored 164 publications receiving 2641 citations.

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Determination of key parameters for SEU occurrence using 3-D full cell SRAM simulations

TL;DR: In this paper, a 3D entire SRAM cell, based on a 0.35-/spl mu/m current CMOS technology, is simulated with a DEVICE simulator, and the transient current resulting from a heavy ion strike in the most sensitive region of the cell is studied as a function of the LET value, the cell layout and the ion penetration depth.
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Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection

TL;DR: Experimental results, obtained on programs running on two different digital boards, built around an 80C51 microcontroller and a 320C50 Digital Signal Processor, illustrate the potentialities of this new strategy based on the injection of bit-flips randomly in time and location.
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Operational SER Calculations on the SAC-C Orbit Using the Multi-Scales Single Event Phenomena Predictive Platform (MUSCA ${\rm SEP}^{3}$ )

TL;DR: In this paper, the Multi-Scales Single Event Phenomena Predictive Platform (MUSCA SEP3) is presented for predicting SEE cross sections or rates and evaluated thanks to on-board operational results on memories from the ICARE experiment (SAC-C mission).
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An empirical model for predicting proton induced upset

TL;DR: In this paper, an empirical model for proton induced single event upset (SEU) is presented based on heavy ion data, and will improve the previous 'two parameters' Bendel model.
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Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits

TL;DR: In this paper, two new CMOS memory cells, called HIT cells, designed to be SEU-immune are presented, which feature better electrical performances and consume less silicon area compared to previously reported design hardened solutions.