Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals. This paper presents PathFinder, a router that balances the goals of performance and routability. PathFinder uses an iterative algorithm that converges to a solution in which all signals are routed while achieving close to the optimal performance allowed by the placement. Routability is achieved by forcing signals to negotiate for a resource and thereby determine which signal needs the resource most. Delay is minimized by allowing the more critical signals a greater say in this negotiation. Because PathFinder requires only a directed graph to describe the architecture of routing resources, it adapts readily to a wide variety of FPGA architectures such as Triptych, Xilinx 3000 and mesh-connected arrays of FPGAs. The results of routing ISCAS benchmarks on the Triptych FPGA architecture show an average increase of only 4.5% in critical path delay over the optimum delay for a placement. Routes of ISCAS benchmarks on the Xilinx 3000 architecture show a greater completion rate than commercial tools, as well as 11% faster implementations.

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PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs

The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.

· Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
· Views of FPGA programming beyond Verilog/VHDL
· Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Interconnect power is dynamic power dissipation due to switching of interconnection capacitances. This paper describes the characterization of interconnect power in a state-of-the-art high-performance microprocessor designed for power efficiency. The analysis showed that interconnect power is over 50% of the dynamic power. Over 90% of the interconnect power is consumed by only 10% of the interconnections. Relations of interconnect power to wire length distribution and hierarchy level of nets were examined. In light of the results, a router's algorithms were modified, to use larger wire spacing and minimal length routing for the high power consuming interconnects. The power-aware router algorithm was tested on synthesized blocks, demonstrating average saving of 14% in the dynamic power consumption without timing degradation or area increase. The results demonstrate the obtainable benefits of tuning physical design algorithms to save power.

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Interconnect-power dissipation in a microprocessor

This paper presents a new logic simulation technique that uses software levelized compiled-code (LCC) for synchronous designs. Three approaches are proposed: C source code, target machine code and interpreted code. The evaluation speed for the software LCC simulator (SSIM) is about 140,000 (gate) evaluations per second using C source code or target machine code, or 50,000 evaluations per second using interpreted code. It is about 40 to 100 times slower than the AIDA hardware LCC simulator, but is about one order of magnitude faster than a traditional software event simulator. For a 32-bit multiplier with gate activity more than 100%, experiments indicate that SSIM runs about 250 to 1,000 times faster than the AIDA event simulator that evaluates about 4,500 gates per second.

SSIM: A Software Levelized Compiled-Code Simulator

A simple algorithm to perform global wiring is described. Repeated iterations of the algorithm tend to improve the quality of wiring by rerouting around congested areas. Various parameters can be set to give preference to short routes or to reduce the time taken by the algorithm. The algorithm has been tried out for several master-slice chips containing up to 3500 cells with good results. The technique is easily extended to standard cell chip design. An implementation for global wiring of a structured custom chip design style is described along with results. The technique is adaptable to higher level packaging such as chips on modules or modules on a board.

A Simple Yet Effective Technique for Global Wiring

Rip-up and reroute strategies can be applied following use of conventional wiring algorithms to calculate paths for residual connections failed by preceding techniques. The removal of blocking wire to allow new path runs inevitably introduces new (reroute) wiring requirements. In this paper we address the performance implications of various rates of success experienced while attempting reroutes. Using statistical approaches, we develop formulas which allow calculation of expected completion rate and computational effort for several types of rip-up and reroute algorithms. It is found that a basic router having modest completion rate behavior can be used to achieve surprisingly high completion rates, with rip-up strategies.

Performance of Interconnection Rip-Up and Reroute Strategies

Parallel processing is being recognized as a practical way to achieve very high performance in logic simulation of large designs. This tutorial summarizes many of the basic methods employed, and estimates attainable throughput. Next, data structuring and processing factors are explored as they impact parallel simulation. Experience indicates that support processing necessary before and after simulation kernel execution can be accelerated using parallel methods. We conclude by suggesting pitfalls to avoid, and discuss future development directions for parallel logic simulation.

Fundamentals of Parallel Logic Simulation

Force-directed placement algorithms are experimentally compared using several sample problems. Significant differences are noted in the computational efficiency of the algorithms, and in the relationship of the placement solution to the routability of the resulting board.

An experimental comparison of force directed placement techniques

This paper presents the necessary and sufficient conditions for routability of a list of two-point nets to be wired in a single row without using vias (single row routing) in a different formulation from that in [9]. These conditions are expressed in terms of left and right block counts (number of left and right blockages that will be encountered by each net if all nets in the list are routed in the same channel) of nets in the net list. An efficient routing algorithm which exploits these necessary and sufficient conditions is presented. Experimental results demonstrating the effectiveness of this algorithm are also given. Possible practical applications exploiting this set of necessary and sufficient conditions are suggested.

A High-Density Multilayer PCB Router Based on Necessary and Sufficient Conditions for Single Row Routing

This paper describes a family of multiprocessor-based accelerated CAD systems applied to electronic computer aided design. It discusses the product requirements, hardware architecture, system software, and principal applications running on the system. It also elaborates on the market and technology factors that influenced the product's development.

Robert J. Smith

Papers

Performance of Interconnection Rip-Up and Reroute Strategies

Fundamentals of Parallel Logic Simulation

An experimental comparison of force directed placement techniques

A High-Density Multilayer PCB Router Based on Necessary and Sufficient Conditions for Single Row Routing

The STE-264 Accelerated Electronic CAD System