A system and method is disclosed for providing dynamic multimedia jitter buffer adjustment for packet-switched networks. The system temporarily stores an amount of incoming data, which is dynamically adjustable, for an amount of time before sending the data out in a more even stream. The system includes a decoder clock, a jitter buffer, a network jitter statistics collector, and a jitter buffer controller. The decoder clock indicates the arrival-time of the data at the system, while the network jitter statistics collector collects the playback-time of that data. By comparing the arrival-time and the playback-time, the jitter buffer controller determines whether the data arrived on schedule. Accordingly, the depth of the jitter buffer can be adjusted to accommodate the late or early arriving data.

System and method for providing multimedia jitter buffer adjustment for packet-switched networks

A memory device controls the flow of data from the memory device to a configurable logic device. This is in contrast to circuits in which a configurable logic device generates a clock signal that controls the flow of data from a memory device to a configurable logic device. In one embodiment, the configurable logic device is a field programmable gate array ('FPGA'). The memory device can provide the configuration data on a serial output lead or a parallel data bus.

System comprising field programmable gate array and intelligent memory

A circuit and method for generating a substantially smooth clock for clocking asynchronous data to a user device. Incoming asynchronous data is stored in an elastic buffer such as a first-in first-out memory. Periodically, an output identifiable bit is read into the memory and a multibit digital signal corresponding to the number of output clock pulses for it to be read out is determined. This signal, which corresponds to the occupancy of the first-in first-out memory, is used to generate an analog voltage which controls a voltage controlled oscillator that provides the substantially smooth clock for reading data out of the first-in first-out memory. The control loop causes the long term rate of the smooth clock to be substantially equal to the incoming asynchronous data rate.

Asynchronous data clock generator

A digitally controlled timing recovery loop is comprised of a digitally controlled Phase Locked Loop (PLL) consisting of a phase detector, loop filter, and voltage controlled oscillator (VCO). The phase detector is a multi-point sampling phase comparator. The loop filter is comprised of a data independent smoothing filter and a command sequencer. The VCO is a digitally controlled ring oscillator with clock phase selection. The timing recovery loop tolerates a relatively large amount of incoming jitter and minimizes data dependent, ISI-induced, intrinsic jitter.

Digitally controlled timing recovery loop

Method and apparatus for providing a sequence of digitized samples to a modem in substantial synchronism with the incoming signal baud rate, but without using a variable sampling frequency. An incoming signal is sampled at a fixed rate, stored temporariy in a buffer memory, and then interpolated using a digital interpolation filter to provide a sequence of interpolated samples that are equivalent to those that wou!d have been obtained if a variable-frequency sampling rate had been used. Any relative delay between the samples supplied to the modem and the baud rate is sensed and accumulated in an up/down counter. Then the accumulated delay stored in the counter is used to control the selection of coefficients for the interpolation filter.

Digital synchronization technique

A circuit for dejittering transmitted digital data. A buffer stores the incoming data and has its half-full condition monitored by content decoding circuitry including a counter whose count is converted to control the frequency of a voltage controlled oscillator. The oscillator clocks the data out of the buffer effectively free of harmful jitter.

Data dejittering apparatus

A real-time error detection system for bi-phase or similarly encoded digital data is disclosed. Bi-phase or similarly encoded data, which utilizes two transitions in a bit cell for either a binary "1" or a binary "0" value, and one transition in a bit cell for the other binary value inherently generates an even number of transitions of the binary value represented by the two transitions between the occurrence of the other binary value represented by one transition. Monitoring for the number of transitions of the binary value represented by two transitions provides an indication of the occurrence of an odd number of transitions. This represents an error condition. The system utilizes a logic circuit responsive to the binary "1" and binary "0" data clock retrieved from the self-clocking bi-phase encoded data. When an error condition is detected, an error indicating signal is generated.

Robert Lee Robinson

Papers

Data dejittering apparatus

Error detection and indication system for bi-phase encoded digital data