A user-removable CPU card includes a microprocessor and a bus bridge memory controller that allows the use of the microprocessor as a central processing unit of an electrical device (e.g. notebook PC or desktop PC). The user-removable CPU card includes a first connector that can be detachably coupled to a second connector in the electrical device, when the user-removable CPU card is inserted through an opening of the electrical device. When the electrical device is powered up subsequent to such insertion, the microprocessor on the user-removable CPU card functions as the central processing unit. Inclusion of a central processing unit of a computing device on a user-removable CPU card allows easy replacement of the CPU, for example, by simply opening a door and operating an eject mechanism, without disassembly of the housing. Therefore, a user can upgrade to a new central processing unit by simply ejecting a previously inserted user-removable CPU card and inserting a new user-removable CPU card, as easily as switching diskettes in the prior art (except for powering up the electrical device after such switching).

User-removable central processing unit card for an electrical device

Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache with a dirty bit asserted, or the data should be written to both the cache and main memory. The write-through method is chosen where the write-through method is approximately as fast as the write-back method. Where the write-back method is substantially faster than the write-through method, the write-back method is chosen.

Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system

A memory controller which can be used with an external tag RAM is disclosed. Existing index registers in the controller serve double duty as buffers for storing tag RAM data during a test mode. Input/output lines for the external tag RAM are coupled to the index registers in addition to being coupled to a comparator for comparison with an external address during normal operation. A buffer is provided so that data from the external address from the CPU can be written through these same tag RAM input/output lines in order to update the tag RAM after a miss. In order to prevent DRAMS from putting data on the memory bus during a cache RAM test, a CAS inhibit signal is provided to the DRAM state machine. Posted writes are also disabled to avoid interference with the address provided to the tag RAM.

Data cache management system with test mode using index registers and CAS disable and posted write disable

A system and method for upgrading a computer is disclosed. Certain essential chips present in the original computer system are functionally, but not physically, removed from the computer system. The functions which would otherwise be performed by the original chips are instead performed by higher-performance chips on a plug-in module which is plugged into the computer system. The functional removal of the certain chips from the original computer system is achieved through simple insertion of the plug-in module. No replacement or substitution of original chips or boards is necessary.

Apparatus for automatically disabling and isolating a computer's original processor upon installation of a processor upgrade card

A system and method for upgrading a computer is disclosed. Certain essential chips present in the original computer system are functionally, but not necessarily physically, removed from the computer system. Functions which would otherwise be performed by the original chips are instead performed by higher-performance chips on a plug-in module which is plugged into the computer system. The functional removal of the certain chips from the original computer system is achieved through simple insertion of the plug-in module. No replacement or substitution of original chips or boards is necessary. Furthermore, upgraded computer systems may be further upgraded by replacement of a first plug-in module with a second plug-in module with different performance characteristics.

Computer system with modular upgrade capability

A method and apparatus for enhancing the speed of operation of a computer consists of providing a cache memory which is faster than the computer's main memory, disabling the computer's main microprocessor, and replacing it with a microprocessor with a faster clock cycle time. A portion of the program stored in the main memory is stored in the cache memory. The addresses of the portion of the main memory stored in the cache memory are noted in a tag RAM. Upon each addressing sequence during the execution of a program, the tag RAM is examined to determine if the addressed located is stored in the cache memory. If the stored location is identified in the tag RAM, it is retrieved from the cache memory at high-speed. Otherwise, the data in the address location is retrieved from main memory at a slower speed and written into the cache memory so that subsequent accesses may be made at high-speed.

Cache memory architecture for microcomputer speed-up board

A system for producing a notification. The system includes a control device that includes a processor, a master clock operably connected to the processor and configured to produce a master clock signal, a user interface operably connected to the processor and configured to generate an operational sequence based upon a user input, and a transmitter operably connected to the processor and configured to transmit the master clock signal and the operational sequence. The system further includes a plurality of output devices configured to establish a connection with the control device, to receive the master clock signal and the operational sequence via the established connection, and to produce a synchronized notification based upon the master clock signal and the operational sequence. The synchronized notification may include flashing lights, audible sounds, or other similar displays.

Robert Mccaslin

Papers

Cache memory architecture for microcomputer speed-up board

Precisely synchronized notification system