Digital tile-based mapping techniques are disclosed that enable efficient online serving of aesthetically pleasing maps. In one particular embodiment, an image tile-based digital mapping system is configured for generating map tiles during an offline session, and serving selected sets of those tiles to a client when requested. Also provided are solutions for handling map labels and other such features in a tile-based mapping system, such as when a map label crosses map tile boundaries. Various processing environments (e.g., servers or other computing devices) can be employed in the system.

Generating and serving tiles in a digital mapping system

A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.

Video and graphics system with parallel processing of graphics windows

A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.

Video, audio and graphics decode, composite and display system

The invention provides a lithographic method referred to as “dip pen” nanolithography (DPN). DPN utilizes a scanning probe microscope (SPM) tip (e.g., an atomic force microscope (AFM) tip) as a “pen,” a solid-state substrate (e.g., gold) as “paper,” and molecules with a chemical affinity for the solid-state substrate as “ink.” Capillary transport of molecules from the SPM tip to the solid substrate is used in DPN to directly write patterns consisting of a relatively small collection of molecules in submicrometer dimensions, making DPN useful in the fabrication of a variety of microscale and nanoscale devices. The invention also provides substrates patterned by DPN, including submicrometer combinatorial arrays, and kits, devices and software for performing DPN. The invention further provides a method of performing AFM imaging in air. The method comprises coating an AFM tip with a hydrophobic compound, the hydrophobic compound being selected so that AFM imaging performed using the coated AFM tip is improved compared to AFM imaging performed using an uncoated AFM tip. Finally, the invention provides AFM tips coated with the hydrophobic compounds.

Methods utilizing scanning probe microscope tips and products therefor or produced thereby

A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.

Video and graphics system with video scaling

In a graphics pipeline, a rasterizer circuit generates fragments for an image having multiple surfaces that have been tessellated into primitive objects, such as triangles. First and second fragments are associated with the same pixel. A merge buffer merges the first fragment with the second fragment when the two fragments belong to the same tessellated surface, the first fragment's primitive is adjacent to the second fragment's primitive, both fragments face either toward or away from the viewer, and the first and second fragment are sufficiently similar that merging is unlikely to introduce visually objectionable artifacts. A frame buffer receives fragments from the merge buffer, stores the fragments, combines the fragments into pixels, and outputs the pixels to a display.

System and method for producing an antialiased image using a merge buffer

High-performance 3D graphics accelerators traditionally require multiple chips on multiple boards, including geometry, rasterizing, pixel processing, and texture mapping chips. These designs are often scalable: they can increase performance by using more chips. Scalability has obvious costs: a minimal configuration needs several chips, and some configurations must replicate texture maps. A less obvious cost is the almost irresistible temptation to replicate chips to increase performance, rather than to design individual chips for higher performance in the first place.In contrast, Neon is a single chip that performs like a multichip design. Neon accelerates OpenGL [19] 3D rendering, as well as X11 [20] and Windows/NT 2D rendering. Since our pin budget limited peak memory bandwidth, we designed Neon from the memory system upward in order to reduce bandwidth requirements. Neon has no special-purpose memories; its eight independent 32-bit memory controllers can access color buffers, Z depth buffers, stencil buffers, and texture data. To fit our gate budget, we shared logic among different operations with similar implementation requirements, and left floating point calculations to Digital's Alpha CPUs. Neon's performance is between HP's Visualize fx4 and fx6, and is well above SGI''s MXE for most operations. Neon-based boards cost much less than these competitors, due to a small part count and use of commodity SDRAMs.

Neon: a single-chip 3D workstation graphics accelerator

Existing techniques for traversing a polygon generate fragments one (or more) rows or columns at a time. (A fragment is all the information needed to paint one pixel of the polygon.) This order is non-optimal for many operations. For example, most frame buffers are tiled into rectangular pages, and there is a cost associated with accessing a different page. Pixel processing is more efficient if all fragments of a polygon on one page are generated before any fragments on a different page. Similarly, texture caches have reduced miss rates if fragments are generated in tiles (and even tiles of tiles) whose size depends upon the cache organization.We describe a polygon traversal algorithm that generates fragments in a tiled fashion. That is, it generates all fragments of a polygon within a rectangle (tile) before generating any fragments in another rectangle. For a single level of tiling, our algorithm requires one additional saved context (the values of all interpolator accumulators, such as Z depth, Red, Green, Blue, etc.) over a traditional traversal algorithm based upon half-plane edge functions. An additional level of tiling requires another saved context for the special case of rectangle copies, or three more for the general case. We describe how to use this algorithm to generate fragments in an optimal order for several common scenarios.

/pdf/tiled-polygon-traversal-using-half-plane-edge-functions-p0g9gyt0c1.pdf

Tiled polygon traversal using half-plane edge functions

A method and apparatus for visiting all stamps that are relevant to a two-dimensional convex polygonal object. The object is visited with a rectangular stamp, which contains one or more discrete sample points. A relevant location is one for which the object contains at least one of the stamp's sample points when the stamp is placed at that location. Stamp locations are discrete points that are separated vertically by the stamp's height, and horizontally by the stamp's width. The stamp may move to a nearby position, or to a previously saved position, as it traverses the object. The plane in which the object lies is partitioned into rectangular tiles, which are at least as wide and high as the stamp. The invention visits stamp locations in an order that respects tile boundaries—that is, it visits all locations within one tile before visiting any locations within another tile. The invention may also be used with further partitioning of the plane (metatiles), so that it will visit all locations within a metatile before visiting any locations within another metatile, and further visit all locations within a portion of a tile within the current metatile before visiting any locations within a portion of a different tile within the current metatile.

Method and apparatus for tiled polygon traversal

A method for improving the performance of a graphics system includes the steps of allocating appropriate pixels to slices of memory such that corresponding subsets of bits of neighboring pixels are allocated to different slices of memory, where `neighboring pixels` includes both consecutive pixels in a scan line, or pixels in consecutive scan lines. In addition, hardware is provided that allows for the individual memory slices to be independently accessed, thus allowed each slice to access data from a different 64 bit word in video memory during one video access period. Controllers which independently access the memory slices are advantageously totally time independent, to allow the most flexibility in the starting and finishing of the access of the memory slice. Performance is further gained by buffering of both the read and write requests to the video memory. Buffering requests allows reads and writes to neighboring locations to be merged to allow for the maximal bus utilization and minimizes the number of stalls in the video subsystem.

Robert S. McNamara

Papers

System and method for producing an antialiased image using a merge buffer

Neon: a single-chip 3D workstation graphics accelerator

Tiled polygon traversal using half-plane edge functions

Method and apparatus for tiled polygon traversal

Method for providing improved graphics performance through atypical pixel storage in video memory