The current status of a research program at Carnegie-Mellon University aimed at the formulation of a hierarchical design methodology for digital VLSI circuits is described In addition, this paper describes a set of computer aids which supports this methodology One of the goals of this work is to provide a design environment which allows for a significant reduction in time between the initial concept of a complex digital system and the generation of masks Another goal is to allow the designer to efficiently explore a number of design alternatives

A design methodology and computer aids for digital VLSI systems

In this paper we describe the quad-CIF tree data structure and its application to hierarchical on-line computer-aided design algorithms. The main idea is to overlay a tree of coordinates on top of the hierarchical representation of an integrated circuit. The coordinate tree enables one to find quickly the set of all objects that intersect a given window. We outline how one can use the data structure in order to implement hierarchical, on-line design rule checking and node extraction. We also describe some applications to plotting.

The Quad-CIF Tree: A Data Structure for Hierarchical On-Line Algorithms

This paper describes the design, implementation and performance of a fiat edge-based circuit extractor for NMOS circuits. The extractor is able to work on large and complex designs, it can handle arbitrary geometry, and outputs a comprehensive wirelist. Measurements show that the run time of the edge-based algorithm used is linear in size of the circuit, with low implementation overheads. The extractor is capable of analyzing a circuit with 20,000 transistors in less than 30 minutes of CPU time on a VAX 11/780. The high performance of the extractor has changed the role that a circuit extractor played in the design process, as it is now possible to extract a chip a number of times during the same session.

ACE: A Circuit Extractor

Metallization for very-large-scale integrated circuits☆

This paper describes an architecture for design rule checking that uses a small amount of special purpose hardware to achieve a significant speed improvement over conventional methods. A fixed grid raster scan algorithm is used that allows checking of 45 ° angled edges at a modest cost in performance. Operations implemented directly in hardware include width checks, edge condition checks, boolean operations on masks, and shrinking and expansion of masks. Hardware support for rasterization is also provided. Software in a controlling processor handles all geometric data manipulation. This architecture should be able to check a simple set of design rules on a 300 mil square layout in one and one half minutes, if the controlling processor can provide data quickly enough. Layouts have been completed for two of four custom chips used in this architecture, and one has been fabricated and proven functional.

A Hardware Assisted Design Rule Check Architecture

: This paper presents a statistical study of the components on VLSI chips. We examine the size and shape of components, and their placement over the chip area. The data is useful for building efficient VLSI design tools: the form of the distribution shows that some simple strategies can lead to efficient algorithms, and the parameters of the distribution aid in choosing program parameters. To illustrate the application of the statistics to VLSI design tasks, we present an algorithm for solving the 'rectangle intersection' problem that arises in design rule checkers. (Author)

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Robert W Hon

Papers

Statistics on VLSI Designs.