The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16 , 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Integrated circuit I/O using a high performance bus interface

Electrical power distribution control methods, electrical energy demand monitoring methods, and power management devices are described. In one aspect, an electrical power distribution control method includes providing electrical energy from an electrical power distribution system, applying the electrical energy to a load, providing a plurality of different values for a threshold at a plurality of moments in time and corresponding to an electrical characteristic of the electrical energy, and adjusting an amount of the electrical energy applied to the load responsive to an electrical characteristic of the electrical energy triggering one of the values of the threshold at the respective moment in time.

Electrical power distribution control methods, electrical energy demand monitoring methods, and power management devices

A microprocessor is disclosed herein having an external command mode for directly accessing the execution unit, responsive to externally generated commands and instructions. An external instruction path is provided, as well as a conventional processor-driven instruction path. A multiplexer is provided that selects which of the instruction paths is actually supplied to the execution unit. Using the external command mode, the user can examine and modify registers, memory, and I/O space without otherwise affecting their contents. Any instruction executable by the execution unit is executable in the external command mode. Because direct access is provided into the execution unit, there is no implicit updating that would otherwise affect the state of the processor and require saving to an alternate memory. The present invention is implemented with a conventional test access port designed in accordance with the IEEE 1149.1 boundary scan standard, with modification to include an instruction register, a data register, and control logic. The external command mode is applicable to single and multiple pipeline processors. The circuit described herein includes several selectors for selecting between the probe mode and the processor-driven mode of operation, including an external pin, an external command, and a debug exception. For ascertaining if the circuit is in the external command mode, an acknowledge pin is provided to indicate when the execution unit is ready to accept an instruction in the probe model.

Microprocessor with an external command mode for diagnosis and debugging

The invention encourages optimal exercise, particularly of the aerobic type, for cardiovascular fitness. The user powers an exerciser, such as a treadmill, simulated cycling or rowing, and the like, and a monitor displays the users speed and distance accomplished. A variable speed outdoor exercising scene (such as a person rowing a boat) is shown to the user when the monitor is a TV set. The users speed signal controls the speed of a videotape cassette player to proportionately change the speed of the outdoor exercising scene. The speed signal is converted to the reciprocal of speed i.e., minutes per mile and the distance is displayed to hundredths of miles. The latter two signals are converted to BCD digits and superimposed on the video through a TV positioning and generation circuit for display on the scene. The heart beat is picked up electrically or by infra red and converted into three digits of beats per minute, and also superimposed on the video for display on the monitor. In addition, the users pulse rate or heart beat is displayed.

Exercise monitor system and method

An interfacing circuitry for a semiconductor circuit of a computer system selects the semiconductor circuit for a device operation in accordance with data, addresses, and control information received from a multiline bus of the computer system in a form of packets. The computer system has a plurality of semiconductor circuits. The interfacing circuitry is coupled to the multiline bus. The multiline bus has a total number of lines less than a total number of bits in any single address. The interfacing circuitry resides inside the semiconductor circuit and includes a decoder for decoding the packets received to identify the data, addresses, and control information. A control logic circuitry is coupled to the decoder circuitry for controlling device operation of the first semiconductor circuit in accordance with the data, addresses, and control information received. A register circuitry is coupled to the decoder and the control logic circuitry for storing a first value corresponding to a first predetermined time period during which the interfacing circuitry must wait before transmitting reply information through the multiline bus in response to the data, addresses, and control information received. The register circuitry applies the first value to the control logic circuitry to cause the control logic circuitry to wait for the first predetermined time period before accessing the multiline bus for transmitting the reply information.

Memory circuitry having bus interface for receiving information in packets and access time registers

A digital system including a plurality of metal-oxide-semiconductor (MOS) chip random access memories (RAM), read only memories (ROM) and peripheral interface adaptors coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU). Each peripheral interface adaptor includes a control register loadable under program control. The contents of the control register control selection of several registers within the interface adaptor. The control register also controls other functions of the peripheral interface adaptor, including determining direction of data movement at the peripheral buffers of the interface adaptor. The contents of the control register of each interface adaptor are monitorable by the microprocessor unit.

Digital data processing system with interface adaptor having programmable monitorable control register therein

Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. This first input is connected to circuitry which is enabled by a signal from a bit of a condition code register on the microprocessor chip which bit, is set, acts to mask or disenable the interrupt signal, so that the instruction execution operation of the microprocessor chip is not interrupted. A second input of a microprocessor chip is adapted to having a second interrupt signal applied thereto. The second input is connected to other input circuitry which is not enabled by the mask bit of a condition code register. Therefore, the second input acts as a non-maskable interrupt input.

Interrupt circuitry for microprocessor chip

A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected to the data bus and the address bus. A peripheral device is connected to an interface adaptor. The interface adaptor is connected to the data bus and the address bus, and performs the function of interfacing between the digital system and a peripheral device, such as a printer or a display device. The microprocessor includes logic circuitry for generating a Valid Memory Address (VMA) output. The VMA output is used to generate an enable signal applied to the memory and the adaptor to enable the memory and the adaptor to be accessed by the microprocessor when the binary address on the address bus is valid and to prevent the memory and the adaptor from being accessed by the microprocessor when the binary address on the address bus is not valid with respect to the microprocessor.

Valid memory address enable system for a microprocessor system

A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between the data bus and a peripheral device, such as a teleprinter. A first interrupt conductor is connected to the peripheral device and to interrupt logic circuitry in the interface adaptor. A second interrupt conductor is connected to the microprocessor and the interrupt logic circuitry. The interrupt logic circuitry is also coupled to and interrogatable by the microprocessor via the data bus. The interrupt logic circuitry stores interrupt contrl information from the data bus, and generates a second interrupt signal on the second interrupt conductor in response to the stored interrupt control information and an interrupt signal generated on the first interrupt conductor by the peripheral device. The interrupt logic circuitry also stores status information indicative of the occurrence of the first interrupt signal and effects interrogation of that status via the data bus.

Interrupt system for microprocessor system

An interface adaptor suitable for use in a microprocessor system includes an input register coupled to a bidirectional data bus of the microprocessor system. The interface adaptor includes a plurality of registers, including a control register and a data register, coupled to the input register by means of an internal input bus. Each of the plurality of registers includes flip-flops which are coupled as slave flip-flops to corresponding flip-flops of the input register. The corresponding flip-flops of the input register function as master flip-flops. The interface adaptor also includes register selection logic circuitry for selecting one of the plurality of registers by electrically coupling its slave flip-flop to the corresponding master flip-flops of the input register.

Rodney H. Orgill

Papers

Digital data processing system with interface adaptor having programmable monitorable control register therein

Interrupt circuitry for microprocessor chip

Valid memory address enable system for a microprocessor system

Interrupt system for microprocessor system

Master slave registers for interface adaptor