A system for calculating the dot product of the vectors A(k) and B(k) of dimension Q written in two's complement representation. A bus has a width sufficient for communicating signals representing a plurality of bit planes A(j,Q) and B(n,Q) corresponding to the two's complement representations of A(k) and B(k), respectively. Circuitry connected to the bus calculates C(j,n)=A(j,Q).B(n,Q) for each of said bit planes. An adder sequentially determines R(n)=C(0,n)2 0 +C(1,n)2 1 + . . . C(N-1,n)2.sup.(N-1) -C(N,n)2 N for n=0,1,2 . . . N. An accumulator connected to the adder shifts and accumulates the R(n)'s to thereby determine the dot product according to: ##EQU1##

Calculating the dot product of large dimensional vectors in two's complement representation

Binary moment diagrams (BMDs) provide a canonical representation for linear functions similar to the way binary decision diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitrary functions from Boolean variables to real, rational, or integer values. BMDs can thus model the functionality of data path circuits operating over word-level data. Many important functions, including integer multiplication, that cannot be represented efficiently at the bit level with BDDs, have simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions as a special case. We propose a hierarchical approach to verifying arithmetic circuits, where component modules are first shown to implement their word-level specifications. The overall circuit functionality is then verified by composing the component functions and comparing the result to the word-level circuit specification. Multipliers with word sizes of up to 256 bits have been verified by this technique.

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Verification of arithmetic circuits using binary moment diagrams

In this paper we present a novel adder/subtracter arithmetic unit that combines binary and binary code decimal (BCD) operations. The proposed unit uses effective addition/subtraction operations on unsigned, sign-magnitude, and various complement representations. Our design overcomes the limitations of previously reported approaches that produce some of the results in complement representation when operating on sign-magnitude numbers. The proposal can be implemented in ASIC as a run time configurable unit as well as in reconfigurable technology in form of a run-time reconfigurable engine. When reconfigurable technology is considered, a preliminary estimation indicates that 40 % of the hardware resources are shared by the different operations. This makes the proposed unit highly suitable for reconfigurable platforms with partial reconfiguration support. The proposed design together with some classical adder organizations were compared after synthesis targeting 4vfx60ff672-12 Xilinx Virtex 4 FPGA. Our design achieves a throughput of 82.6 MOPS with almost equivalent area-time product when compared to the other proposals.

Reconfigurable Universal Adder

Fast Fourier Transform (FFT) and Discrete Cosine Transform (DCT) processors are designed and implemented using a Xilinx Field Programmable Gate Array (FPGA) device XC 4010. This device allows a 16-point FFT/DCT processor implementation. To design the CLB-efficient FFT/DCT processor in FPGAs, a pipelined bit-serial architecture with bit-parallel input data format is employed. These processors operate with a 20 MHz bit-clock and 16-bit system word length, and compute an entire 16-point DFT/DCT transform for every 16-bit clock cycle.

Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs

The implementation of finite impulse response (FIR) digital filters using pipelined bit-serial arithmetic and canonic signed digit (CSD) coefficient coding can be an effective use of hardware resources. However, the necessary time alignment of all data and control signals can be a tedious process. A methodology for implementing FIR filters using pipelined bit-serial arithmetic and field programmable gate arrays (FPGAs) is described.

Roelof Maarten Marie Oberman

Papers

Digital Circuits for Binary Arithmetic