In a MOS solid-state image pickup device including two capacitors storing electric charges of pixels in two rows for each column and two charge-voltage conversion amplifiers for outputting pixel signals corresponding to the electric charges stored in the capacitors, a switch for selectively short-circuiting input terminals of the charge-voltage conversion amplifiers and a switch for short-circuiting output terminals of the charge-voltage amplifiers are provided. In a first driving mode, the switches are not short-circuited so that analog signals are read in the form of dual-rail outputs. In a second driving mode, the switches are short-circuited so that an average of the analog signals is read.

Solid-state image pickup device and driving method therefor

Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.

Double gated transistor and method of fabrication

An image sensor is reduced in size by combining a photoelectric conversion element with a transfer element thin film transistor (TFT). The photoelectric conversion element comprises a lamination including a metal electrode, a photoconductive layer and a transparent electrode. The TFT transfer element comprises a gate electrode, a drain electrode and a source electrode. In the image sensor, the metal electrode of the photoelectric conversion element also serves as the drain electrode of the TFT. In addition, the gate electrode is formed around the photoelectric conversion element, and the source electrode is formed around the gate electrode.

Image sensor having TFT gate electrode surrounding the photoelectric conversion element

A new integrated circuit structure which includes two types of active devices: a first set of IGFETs has silicide gates, and the second set has TiN gates. The same TiN thin film layer also provides local interconnect. Optionally the TiN-gate devices may be used for high-voltage devices and the silicide-gate devices used for logic devices.

Integrated circuit device and process with tin-gate transistor

A diffusionless source/drain conductor, electrically-erasable, electrically-programmable read-only memory cell is formed at a face of a semiconductor layer (38) of a first conductivity type and includes a source conductor (10), a drain conductor (12), a channel region (18), and a tunnel region (22). Source conductor (10) and drain conductor (12) are disposed to create inversion regions, of a second conductivity type, opposite said first conductivity type, in the source inversion region (14) and drain inversion region (16) of semiconductor layer (38) of the layer semiconductor, upon application of voltage. Thin oxide tunneling window (22) is disposed adjacent source conductor (10). A floating gate (24) disposed adjacent tunneling window can be charged or discharged by Fowler-Nordheim tunneling when a voltage is applied between the inversion created in source inversion region (14) and a control gate (26) insulatively adjacent floating gate (24).

Diffusionless source/drain conductor electrically-erasable, electrically-programmable read-only memory and methods for making and using the same

A P-channel MOS double gated transistor is provided with an electrical shield element located between the drain and the second gate. The shield is electrically connected to the first gate and is dc biased by the first gate control voltage at FIRST GATE SELECT. The presence of the first gate control voltage causes all the shield capacitances to charge and causes a depletion region between the shield and the drain. Prior to SECOND GATE SELECT, the electrical transient effects of activating the shield with a dc bias have expired. SECOND GATE SELECT introduces new transients (noise current), noteable charging of the capacitance between the drain and the second gate and formation of the final section of depletion region proximate the second gate completing the P channel. This capacitance is drastically reduced by the intervening shield, and the depletion transient is minimized by the priming depletion region established by the shield voltage.

Roger D. Melen

Papers

Low transient effect switching device and method