A comprehensive review of printed circuit board (PCB) electromagnetic compatibility (EMC) issues, analysis techniques, and possible solutions would fill a large book or more. This review takes a quick look at where the technology of PCB EMC control has been, where it is today, and where it needs to go for the future. As data rates on PCBs have increased, new problems have arisen, requiring new analysis techniques and new solutions. Further development will be needed to keep up with the ever-increasing data rates and smaller form factors.

Review of Printed-Circuit-Board Level EMI/EMC Issues and Tools

In printed circuit board (PCB) designs, it is common to split power/ground planes into different partitions, which leads to more crosstalk among signal traces that route crossing a split. It is of general interest to develop a crosstalk model for various geometric parameters. However, the long time required to simulate the structure with any given set of geometric parameters renders general modelling approaches such as interpolation inefficient. In this paper, we develop an empirical model based upon the compressed sensing technique to characterize the crosstalk among traces as a function of geometric parameters. A good agreement between the empirical model and full-wave simulations is observed for various test examples, with an exceptionally small number of samples.

Estimation of crosstalk among multiple stripline traces crossing a split by compressed sensing

Under the platform of a high-speed package system, a modeling method considering all the significant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity(SI/PI). For SI issues, accurate modelings for signal channel are verified by system of high speed line. The following what-if analyses help to identify the package trace's bottlenecks and have great effects on signal transmission. For PI part, the modeling methodologies for power distribution networks of data line are demonstrated and validated with the results of frequency domain simulation. Lastly, with the co-simulations by chip-package-PCB model, the paper was talked about the SI and PI problem using SI-PI co-analysis methodology. The analysis results indicates that the parasitic effects of the high speed package system are the most critical, depicting the importance of improved package design in the next high speed package system.

Signal-power integrity co-simulations of high speed systems via chip-package-PCB co-analysis methodology

Power and/or ground splits and slots frequently arise in real-world boards to manage the various constraints placed on the board designer. As a consequence, signal traces can often be forced to cross these plane split and slot boundaries or routed in close proximity to them. These trace routes may have a number of undesirable consequences on both signal integrity and power integrity. In this paper, we will examine the impact of split and slotted planes using both measured and simulated data.

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Roger Dame

Papers

Examining the Impact of Split Planes on Signal and Power Integrity